diff --git a/src/nouveau/compiler/nak/assign_regs.rs b/src/nouveau/compiler/nak/assign_regs.rs
index 4a262c08a46..c662877cb9d 100644
--- a/src/nouveau/compiler/nak/assign_regs.rs
+++ b/src/nouveau/compiler/nak/assign_regs.rs
@@ -307,9 +307,7 @@ impl RegAllocator {
     }
 
     pub fn try_get_vec_reg(&self, vec: &SSARef) -> Option<u32> {
-        let Some(reg) = self.try_get_reg(vec[0]) else {
-            return None;
-        };
+        let reg = self.try_get_reg(vec[0])?;
 
         let align = u32::from(vec.comps()).next_power_of_two();
         if reg % align != 0 {
diff --git a/src/nouveau/compiler/nak/ir.rs b/src/nouveau/compiler/nak/ir.rs
index 83d8686859b..b3adedf36f5 100644
--- a/src/nouveau/compiler/nak/ir.rs
+++ b/src/nouveau/compiler/nak/ir.rs
@@ -4627,17 +4627,12 @@ impl OpPrmt {
     }
 
     pub fn as_u32(&self) -> Option<u32> {
-        let Some(sel) = self.get_sel() else {
-            return None;
-        };
+        let sel = self.get_sel()?;
 
         let mut imm = 0_u32;
         for b in 0..4 {
             let sel_byte = sel.get(b);
-            let sel_src = &self.srcs[sel_byte.src()];
-            let Some(src_u32) = sel_src.as_u32(SrcType::ALU) else {
-                return None;
-            };
+            let src_u32 = self.srcs[sel_byte.src()].as_u32(SrcType::ALU)?;
 
             let sb = sel_byte.fold_u32(src_u32);
             imm |= u32::from(sb) << (b * 8);