diff --git a/src/freedreno/ci/freedreno-a750-fails.txt b/src/freedreno/ci/freedreno-a750-fails.txt
index a11293f501d..10a03198d88 100644
--- a/src/freedreno/ci/freedreno-a750-fails.txt
+++ b/src/freedreno/ci/freedreno-a750-fails.txt
@@ -35,10 +35,6 @@ dynamic-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_s
 spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_yvu420,Fail
 
 # New fails in 1.4.3.3
-dEQP-VK.transform_feedback.primitive_restart.dynamic_primitive_restart_dynamic_primitive_topology,Fail
-dEQP-VK.transform_feedback.primitive_restart.dynamic_primitive_restart_static_primitive_topology,Fail
-dEQP-VK.transform_feedback.primitive_restart.static_primitive_restart_dynamic_primitive_topology,Fail
-dEQP-VK.transform_feedback.primitive_restart.static_primitive_restart_static_primitive_topology,Fail
 dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_16,Fail
 dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_244,Fail
 dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_508,Fail
diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h
index 8b14b648ecf..60eaf0ee49d 100644
--- a/src/freedreno/common/freedreno_dev_info.h
+++ b/src/freedreno/common/freedreno_dev_info.h
@@ -272,6 +272,9 @@ struct fd_dev_info {
        * that can be written by CP_REG_TEST instead of just 1.
        */
       bool has_pred_bit;
+
+      /* True if PC_DGEN_SO_CNTL is present. */
+      bool has_pc_dgen_so_cntl;
    } a6xx;
 
    struct {
diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index 62633dadfed..f09c781ce70 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -408,6 +408,7 @@ a6xx_gen3 = A6XXProps(
         has_early_preamble = True,
         prede_nop_quirk = True,
         has_pred_bit = True,
+        has_pc_dgen_so_cntl = True,
     )
 
 a6xx_gen4 = A6XXProps(
@@ -445,6 +446,7 @@ a6xx_gen4 = A6XXProps(
         has_sad = True,
         has_sel_b_fneg = True,
         has_pred_bit = True,
+        has_pc_dgen_so_cntl = True,
     )
 
 add_gpus([
@@ -927,6 +929,7 @@ a7xx_base = A6XXProps(
         has_bin_mask = True,
         has_sel_b_fneg = True,
         has_pred_bit = True,
+        has_pc_dgen_so_cntl = True,
     )
 
 a7xx_gen1 = A7XXProps(
diff --git a/src/freedreno/vulkan/tu_pipeline.cc b/src/freedreno/vulkan/tu_pipeline.cc
index 6b0e93b4a8b..00eaf574d8c 100644
--- a/src/freedreno/vulkan/tu_pipeline.cc
+++ b/src/freedreno/vulkan/tu_pipeline.cc
@@ -494,13 +494,14 @@ tu6_setup_streamout(struct tu_cs *cs,
 #define A6XX_SO_PROG_DWORDS 64
    uint32_t prog[A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS] = {};
    BITSET_DECLARE(valid_dwords, A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS) = {0};
+   bool has_pc_dgen_so_cntl = cs->device->physical_device->info->a6xx.has_pc_dgen_so_cntl;
 
    /* TODO: streamout state should be in a non-GMEM draw state */
 
    /* no streamout: */
    if (info->num_outputs == 0) {
       unsigned sizedw = 4;
-      if (cs->device->physical_device->info->a6xx.tess_use_shared)
+      if (has_pc_dgen_so_cntl)
          sizedw += 2;
 
       tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, sizedw);
@@ -509,7 +510,7 @@ tu6_setup_streamout(struct tu_cs *cs,
       tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
       tu_cs_emit(cs, 0);
 
-      if (cs->device->physical_device->info->a6xx.tess_use_shared) {
+      if (has_pc_dgen_so_cntl) {
          tu_cs_emit(cs, REG_A6XX_PC_DGEN_SO_CNTL);
          tu_cs_emit(cs, 0);
       }
@@ -562,11 +563,7 @@ tu6_setup_streamout(struct tu_cs *cs,
       prog_count += end - start + 1;
    }
 
-   const bool emit_pc_so_stream_cntl =
-      cs->device->physical_device->info->a6xx.tess_use_shared &&
-      v->type == MESA_SHADER_TESS_EVAL;
-
-   if (emit_pc_so_stream_cntl)
+   if (has_pc_dgen_so_cntl)
       prog_count += 1;
 
    tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 10 + 2 * prog_count);
@@ -597,9 +594,9 @@ tu6_setup_streamout(struct tu_cs *cs,
       first = false;
    }
 
-   if (emit_pc_so_stream_cntl) {
-      /* Possibly not tess_use_shared related, but the combination of
-       * tess + xfb fails some tests if we don't emit this.
+   if (has_pc_dgen_so_cntl) {
+      /* When present, setting this register makes sure that degenerate primitives
+       * are included in the stream output and not discarded.
        */
       tu_cs_emit(cs, REG_A6XX_PC_DGEN_SO_CNTL);
       tu_cs_emit(cs, A6XX_PC_DGEN_SO_CNTL_STREAM_ENABLE(info->streams_written));