From b98a7abcd69240a14fadedf96c016f1dac7eb2a9 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 12 Feb 2024 14:44:58 +0100 Subject: [PATCH] radv: determine the ES stage for merged NGG shaders compiled separately Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_pipeline_graphics.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index e404f21004f..58cd2758fe6 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -2955,9 +2955,19 @@ radv_emit_hw_ngg(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, { const struct radv_physical_device *pdevice = device->physical_device; uint64_t va = radv_shader_get_va(shader); - gl_shader_stage es_type = shader->info.stage == MESA_SHADER_GEOMETRY ? shader->info.gs.es_type : shader->info.stage; + gl_shader_stage es_type; const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info; + if (shader->info.stage == MESA_SHADER_GEOMETRY) { + if (shader->info.merged_shader_compiled_separately) { + es_type = es->info.stage; + } else { + es_type = shader->info.gs.es_type; + } + } else { + es_type = shader->info.stage; + } + radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);