From b9656d51c0057321fc9184309319dd3f269d7451 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Wed, 12 Feb 2025 10:15:15 -0800 Subject: [PATCH] brw/opt: Move non-SSA register accounting after first brw_opt_split_virtual_grfs v2: Move to immediately before the main optimization loop. Most importantly, this is after the first call to DCE. fossil-db: All Intel platforms had similar results. (Lunar Lake shown) Totals: Non SSA regs after NIR: 237045283 -> 100183460 (-57.74%); split: -58.12%, +0.39% Totals from 701423 (99.26% of 706657) affected shaders: Non SSA regs after NIR: 236868848 -> 100007025 (-57.78%); split: -58.17%, +0.39% Suggested-by: Ken Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/brw_opt.cpp | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/intel/compiler/brw_opt.cpp b/src/intel/compiler/brw_opt.cpp index dca507cdc89..5dd4d833cd2 100644 --- a/src/intel/compiler/brw_opt.cpp +++ b/src/intel/compiler/brw_opt.cpp @@ -19,13 +19,6 @@ brw_optimize(brw_shader &s) /* Start by validating the shader we currently have. */ brw_validate(s); - /* Track how much non-SSA at this point. */ - { - const brw_def_analysis &defs = s.def_analysis.require(); - s.shader_stats.non_ssa_registers_after_nir = - defs.count() - defs.ssa_count(); - } - bool progress = false; int iteration = 0; int pass_num = 0; @@ -60,6 +53,13 @@ brw_optimize(brw_shader &s) OPT(brw_opt_eliminate_find_live_channel); + /* Track how much non-SSA at this point. */ + { + const brw_def_analysis &defs = s.def_analysis.require(); + s.shader_stats.non_ssa_registers_after_nir = + defs.count() - defs.ssa_count(); + } + do { progress = false; pass_num = 0;