From b848fa45959b0455db8cea8350560902769717c6 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 31 Jan 2025 02:47:53 -0800 Subject: [PATCH] brw: Rename is_send_from_grf to is_send, replace other is_send() helper The is_send() helper is just a wrapper around inst->is_send_from_grf() now, so we can combine the two. Trim the name from is_send_from_grf() to is_send(), as it's shorter, and also matches is_math(). Reviewed-by: Lionel Landwerlin Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/brw_analysis_performance.cpp | 2 +- src/intel/compiler/brw_inst.cpp | 4 ++-- src/intel/compiler/brw_inst.h | 10 ++-------- src/intel/compiler/brw_lower_regioning.cpp | 4 ++-- src/intel/compiler/brw_lower_scoreboard.cpp | 6 +++--- src/intel/compiler/brw_opt_copy_propagation.cpp | 5 ++--- src/intel/compiler/brw_workaround.cpp | 2 +- 7 files changed, 13 insertions(+), 20 deletions(-) diff --git a/src/intel/compiler/brw_analysis_performance.cpp b/src/intel/compiler/brw_analysis_performance.cpp index d40d3aa3d61..a114992adde 100644 --- a/src/intel/compiler/brw_analysis_performance.cpp +++ b/src/intel/compiler/brw_analysis_performance.cpp @@ -946,7 +946,7 @@ namespace { execute_instruction(st, perf); /* Mark any source dependencies. */ - if (inst->is_send_from_grf()) { + if (inst->is_send()) { for (unsigned i = 0; i < inst->sources; i++) { if (inst->is_payload(i)) { for (unsigned j = 0; j < regs_read(devinfo, inst, i); j++) diff --git a/src/intel/compiler/brw_inst.cpp b/src/intel/compiler/brw_inst.cpp index 362ee262a24..f217a64945e 100644 --- a/src/intel/compiler/brw_inst.cpp +++ b/src/intel/compiler/brw_inst.cpp @@ -168,7 +168,7 @@ brw_inst::resize_sources(uint8_t num_sources) } bool -brw_inst::is_send_from_grf() const +brw_inst::is_send() const { switch (opcode) { case SHADER_OPCODE_SEND: @@ -259,7 +259,7 @@ brw_inst::is_payload(unsigned arg) const bool brw_inst::can_do_source_mods(const struct intel_device_info *devinfo) const { - if (is_send_from_grf()) + if (is_send()) return false; /* From TGL PRM Vol 2a Pg. 1053 and Pg. 1069 MAD and MUL Instructions: diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 7d60b614ef8..2240929eddd 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -64,7 +64,7 @@ public: void resize_sources(uint8_t num_sources); - bool is_send_from_grf() const; + bool is_send() const; bool is_payload(unsigned arg) const; bool is_partial_write(unsigned grf_size = REG_SIZE) const; unsigned components_read(unsigned i) const; @@ -330,12 +330,6 @@ get_exec_type_size(const brw_inst *inst) return brw_type_size_bytes(get_exec_type(inst)); } -static inline bool -is_send(const brw_inst *inst) -{ - return inst->is_send_from_grf(); -} - /** * Return whether the instruction isn't an ALU instruction and cannot be * assumed to complete in-order. @@ -343,7 +337,7 @@ is_send(const brw_inst *inst) static inline bool is_unordered(const intel_device_info *devinfo, const brw_inst *inst) { - return is_send(inst) || (devinfo->ver < 20 && inst->is_math()) || + return inst->is_send() || (devinfo->ver < 20 && inst->is_math()) || inst->opcode == BRW_OPCODE_DPAS || (devinfo->has_64bit_float_via_math_pipe && (get_exec_type(inst) == BRW_TYPE_DF || diff --git a/src/intel/compiler/brw_lower_regioning.cpp b/src/intel/compiler/brw_lower_regioning.cpp index 7a1c3c8dbce..8f4172f7f43 100644 --- a/src/intel/compiler/brw_lower_regioning.cpp +++ b/src/intel/compiler/brw_lower_regioning.cpp @@ -316,7 +316,7 @@ namespace { return true; } - if (is_send(inst) || inst->is_control_source(i) || + if (inst->is_send() || inst->is_control_source(i) || inst->opcode == BRW_OPCODE_DPAS) { return false; } @@ -360,7 +360,7 @@ namespace { has_invalid_dst_region(const intel_device_info *devinfo, const brw_inst *inst) { - if (is_send(inst)) { + if (inst->is_send()) { return false; } else if (devinfo->has_bfloat16 && has_bfloat_operands(inst)) { diff --git a/src/intel/compiler/brw_lower_scoreboard.cpp b/src/intel/compiler/brw_lower_scoreboard.cpp index b7c43f63158..042b6a4d75b 100644 --- a/src/intel/compiler/brw_lower_scoreboard.cpp +++ b/src/intel/compiler/brw_lower_scoreboard.cpp @@ -75,7 +75,7 @@ namespace { bool has_int_src = false, has_long_src = false; const bool has_long_pipe = !devinfo->has_64bit_float_via_math_pipe; - if (is_send(inst)) + if (inst->is_send()) return TGL_PIPE_NONE; for (unsigned i = 0; i < inst->sources; i++) { @@ -992,7 +992,7 @@ namespace { return find_unordered_dependency(deps, TGL_SBID_SET, exec_all); else if (has_ordered && is_unordered(devinfo, inst)) return TGL_SBID_NULL; - else if (is_send(inst) && devinfo->ver >= 20) + else if (inst->is_send() && devinfo->ver >= 20) return TGL_SBID_NULL; else if (find_unordered_dependency(deps, TGL_SBID_DST, exec_all) && (!has_ordered || ordered_pipe == inferred_sync_pipe(devinfo, inst))) @@ -1030,7 +1030,7 @@ namespace { return ordered_pipe == inferred_pipe && unordered_mode & (is_unordered(devinfo, inst) ? TGL_SBID_SET : TGL_SBID_DST); - else if (is_send(inst)) + else if (inst->is_send()) return unordered_mode & TGL_SBID_SET && (ordered_pipe == TGL_PIPE_FLOAT || ordered_pipe == TGL_PIPE_INT || diff --git a/src/intel/compiler/brw_opt_copy_propagation.cpp b/src/intel/compiler/brw_opt_copy_propagation.cpp index 43edfa2e90a..4b4f8944ee5 100644 --- a/src/intel/compiler/brw_opt_copy_propagation.cpp +++ b/src/intel/compiler/brw_opt_copy_propagation.cpp @@ -759,8 +759,7 @@ try_copy_propagate(brw_shader &s, brw_inst *inst, /* Reject cases that would violate register regioning restrictions. */ if ((entry->src.file == UNIFORM || !entry->src.is_contiguous()) && - (inst->is_send_from_grf() || - inst->uses_indirect_addressing())) { + (inst->is_send() || inst->uses_indirect_addressing())) { return false; } @@ -1655,7 +1654,7 @@ try_copy_propagate_def(brw_shader &s, assert(inst->src[arg].stride == 0); } else if ((val.file == UNIFORM || !val.is_contiguous()) && - (inst->is_send_from_grf() || inst->uses_indirect_addressing())) { + (inst->is_send() || inst->uses_indirect_addressing())) { return false; } diff --git a/src/intel/compiler/brw_workaround.cpp b/src/intel/compiler/brw_workaround.cpp index 92fd303bf1b..56fae704171 100644 --- a/src/intel/compiler/brw_workaround.cpp +++ b/src/intel/compiler/brw_workaround.cpp @@ -228,7 +228,7 @@ brw_workaround_nomask_control_flow(brw_shader &s) * safely omit the predication for. */ if (depth && inst->force_writemask_all && - is_send(inst) && !inst->predicate && + inst->is_send() && !inst->predicate && !inst->has_no_mask_send_params) { /* We need to load the execution mask into the flag register by * using a builder with channel group matching the whole shader