From b7c0863b97db9acf944c4dc104d60c67c24de6d8 Mon Sep 17 00:00:00 2001
From: Simon Perretta <simon.perretta@imgtec.com>
Date: Wed, 8 Jan 2025 16:49:17 +0000
Subject: [PATCH] pco: add uadd64_32 op

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
---
 src/compiler/nir/nir_lower_alu_width.c |  1 +
 src/compiler/nir/nir_opcodes.py        |  6 ++++++
 src/imagination/pco/pco_trans_nir.c    | 21 +++++++++++++++++++++
 3 files changed, 28 insertions(+)

diff --git a/src/compiler/nir/nir_lower_alu_width.c b/src/compiler/nir/nir_lower_alu_width.c
index 03857ecedff..64d6e469cb9 100644
--- a/src/compiler/nir/nir_lower_alu_width.c
+++ b/src/compiler/nir/nir_lower_alu_width.c
@@ -272,6 +272,7 @@ lower_alu_instr_width(nir_builder *b, nir_instr *instr, void *_data)
    case nir_op_unpack_unorm_2x16:
    case nir_op_unpack_snorm_2x16:
    case nir_op_mqsad_4x8:
+   case nir_op_uadd64_32:
       /* There is no scalar version of these ops, unless we were to break it
        * down to bitshifts and math (which is definitely not intended).
        */
diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py
index 8664904ea55..9436b6983fa 100644
--- a/src/compiler/nir/nir_opcodes.py
+++ b/src/compiler/nir/nir_opcodes.py
@@ -637,6 +637,12 @@ binop("isub_sat", tint, "", """
 """)
 binop("usub_sat", tuint, "", "src0 < src1 ? 0 : src0 - src1")
 
+opcode("uadd64_32", 2, tuint32, [1, 1, 1], [tuint32, tuint32, tuint32], False, "", """
+uint64_t sum = ((uint64_t)src1.x << 32 | (uint64_t)src0.x) + (uint64_t)src2.x;
+dst.x = sum & 0xffffffff;
+dst.y = sum >> 32;
+""")
+
 binop("fsub", tfloat, "", """
 if (nir_is_rounding_mode_rtz(execution_mode, bit_size)) {
    if (bit_size == 64)
diff --git a/src/imagination/pco/pco_trans_nir.c b/src/imagination/pco/pco_trans_nir.c
index 422e8992e73..bc9fd91d11d 100644
--- a/src/imagination/pco/pco_trans_nir.c
+++ b/src/imagination/pco/pco_trans_nir.c
@@ -1394,6 +1394,27 @@ static pco_instr *trans_alu(trans_ctx *tctx, nir_alu_instr *alu)
       instr = pco_iadd32(&tctx->b, dest, src[0], src[1], pco_ref_null());
       break;
 
+   case nir_op_uadd64_32: {
+      pco_ref dest_comps[2] = {
+         [0] = pco_ref_new_ssa32(tctx->func),
+         [1] = pco_ref_new_ssa32(tctx->func),
+      };
+
+      pco_add64_32(&tctx->b,
+                   dest_comps[0],
+                   dest_comps[1],
+                   src[0],
+                   src[1],
+                   src[2],
+                   pco_ref_null());
+
+      /* TODO: mark this vec as being non-contiguous,
+       * add pass for expanding.
+       */
+      instr = pco_trans_nir_vec(tctx, dest, 2, dest_comps);
+      break;
+   }
+
    case nir_op_imul:
       instr = pco_imul32(&tctx->b, dest, src[0], src[1], pco_ref_null());
       break;