From b78835de134e95fc220abacf48452a73b711dbfa Mon Sep 17 00:00:00 2001 From: Mike Blumenkrantz Date: Wed, 12 Feb 2025 10:33:12 -0500 Subject: [PATCH] radv: move non_trivial_format calc to dynamic VI bind this otherwise gets pointlessly recalculated on every draw when a VBO changes another 10% for vkoverhead@draw_vbo_change_dynamic Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 32 ++++++++++--------------- src/amd/vulkan/radv_pipeline_graphics.c | 10 +++++++- src/amd/vulkan/radv_shader.h | 1 + 3 files changed, 23 insertions(+), 20 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 33eb4caa4fc..73aaeddad77 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -5794,8 +5794,6 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag ALWAYS_INLINE void radv_get_vbo_info(const struct radv_cmd_buffer *cmd_buffer, uint32_t idx, struct radv_vbo_info *vbo_info) { - const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - const struct radv_physical_device *pdev = radv_device_physical(device); const struct radv_vertex_input_state *vi_state = &cmd_buffer->state.vertex_input; const uint32_t binding = vi_state->bindings[idx]; @@ -5807,22 +5805,7 @@ radv_get_vbo_info(const struct radv_cmd_buffer *cmd_buffer, uint32_t idx, struct vbo_info->attrib_offset = vi_state->offsets[idx]; vbo_info->attrib_index_offset = vi_state->attrib_index_offset[idx]; vbo_info->attrib_format_size = vi_state->format_sizes[idx]; - - if (!(vi_state->nontrivial_formats & BITFIELD_BIT(idx))) { - const struct ac_vtx_format_info *vtx_info_table = - ac_get_vtx_format_info_table(pdev->info.gfx_level, pdev->info.family); - const struct ac_vtx_format_info *vtx_info = &vtx_info_table[vi_state->formats[idx]]; - const uint32_t hw_format = vtx_info->hw_format[vtx_info->num_channels - 1]; - - if (pdev->info.gfx_level >= GFX10) { - vbo_info->non_trivial_format = vtx_info->dst_sel | S_008F0C_FORMAT_GFX10(hw_format); - } else { - vbo_info->non_trivial_format = - vtx_info->dst_sel | S_008F0C_NUM_FORMAT((hw_format >> 4) & 0x7) | S_008F0C_DATA_FORMAT(hw_format & 0xf); - } - } else { - vbo_info->non_trivial_format = 0; - } + vbo_info->non_trivial_format = vi_state->non_trivial_format[idx]; } ALWAYS_INLINE static void @@ -8435,8 +8418,19 @@ radv_CmdSetVertexInputEXT(VkCommandBuffer commandBuffer, uint32_t vertexBindingD if (G_008F0C_DST_SEL_X(vtx_info->dst_sel) == V_008F0C_SQ_SEL_Z) vi_state->post_shuffle |= BITFIELD_BIT(loc); - if (!(vtx_info->has_hw_format & BITFIELD_BIT(vtx_info->num_channels - 1))) + if (vtx_info->has_hw_format & BITFIELD_BIT(vtx_info->num_channels - 1)) { + const uint32_t hw_format = vtx_info->hw_format[vtx_info->num_channels - 1]; + + if (pdev->info.gfx_level >= GFX10) { + vi_state->non_trivial_format[loc] = vtx_info->dst_sel | S_008F0C_FORMAT_GFX10(hw_format); + } else { + vi_state->non_trivial_format[loc] = + vtx_info->dst_sel | S_008F0C_NUM_FORMAT((hw_format >> 4) & 0x7) | S_008F0C_DATA_FORMAT(hw_format & 0xf); + } + } else { + vi_state->non_trivial_format[loc] = 0; vi_state->nontrivial_formats |= BITFIELD_BIT(loc); + } if (state->vbo_bound_mask & BITFIELD_BIT(attrib->binding)) { uint32_t stride = binding->stride; diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 3cfdf5553ad..74f1379a350 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -3195,6 +3195,7 @@ radv_pipeline_init_vertex_input_state(const struct radv_device *device, struct r enum pipe_format format = radv_format_to_pipe_format(state->vi->attributes[i].format); const struct ac_vtx_format_info *vtx_info = &vtx_info_table[format]; + const uint32_t hw_format = vtx_info->hw_format[vtx_info->num_channels - 1]; pipeline->vertex_input.formats[i] = format; uint8_t format_align_req_minus_1 = vtx_info->chan_byte_size >= 4 ? 3 : (vtx_info->element_size - 1); @@ -3209,7 +3210,14 @@ radv_pipeline_init_vertex_input_state(const struct radv_device *device, struct r pipeline->vertex_input.post_shuffle |= BITFIELD_BIT(i); } - if (!(vtx_info->has_hw_format & BITFIELD_BIT(vtx_info->num_channels - 1))) { + if (vtx_info->has_hw_format & BITFIELD_BIT(vtx_info->num_channels - 1)) { + if (pdev->info.gfx_level >= GFX10) { + pipeline->vertex_input.non_trivial_format[i] = vtx_info->dst_sel | S_008F0C_FORMAT_GFX10(hw_format); + } else { + pipeline->vertex_input.non_trivial_format[i] = + vtx_info->dst_sel | S_008F0C_NUM_FORMAT((hw_format >> 4) & 0x7) | S_008F0C_DATA_FORMAT(hw_format & 0xf); + } + } else { pipeline->vertex_input.nontrivial_formats |= BITFIELD_BIT(i); } } diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 90bcf4377fb..4b401e4900d 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -312,6 +312,7 @@ struct radv_vertex_input_state { uint8_t component_align_req_minus_1[MAX_VERTEX_ATTRIBS]; uint8_t format_sizes[MAX_VERTEX_ATTRIBS]; uint32_t attrib_index_offset[MAX_VERTEX_ATTRIBS]; /* Only used with static strides. */ + uint32_t non_trivial_format[MAX_VERTEX_ATTRIBS]; bool bindings_match_attrib; };