diff --git a/src/gallium/drivers/panfrost/pan_cmdstream.c b/src/gallium/drivers/panfrost/pan_cmdstream.c
index 0b76f524b2d..fdfe983d06e 100644
--- a/src/gallium/drivers/panfrost/pan_cmdstream.c
+++ b/src/gallium/drivers/panfrost/pan_cmdstream.c
@@ -73,7 +73,7 @@ struct panfrost_zsa_state {
struct panfrost_sampler_state {
struct pipe_sampler_state base;
- struct mali_midgard_sampler_packed hw;
+ struct mali_sampler_packed hw;
};
/* Misnomer: Sampler view corresponds to textures, not samplers */
@@ -81,7 +81,7 @@ struct panfrost_sampler_state {
struct panfrost_sampler_view {
struct pipe_sampler_view base;
struct panfrost_pool_ref state;
- struct mali_bifrost_texture_packed bifrost_descriptor;
+ struct mali_texture_packed bifrost_descriptor;
mali_ptr texture_bo;
uint64_t modifier;
};
@@ -123,21 +123,26 @@ translate_tex_wrap(enum pipe_tex_wrap w, bool using_nearest)
/* Bifrost doesn't support the GL_CLAMP wrap mode, so instead use
* CLAMP_TO_EDGE and CLAMP_TO_BORDER. On Midgard, CLAMP is broken for
* nearest filtering, so use CLAMP_TO_EDGE in that case. */
- bool supports_clamp = (PAN_ARCH <= 5);
switch (w) {
case PIPE_TEX_WRAP_REPEAT: return MALI_WRAP_MODE_REPEAT;
case PIPE_TEX_WRAP_CLAMP:
return using_nearest ? MALI_WRAP_MODE_CLAMP_TO_EDGE :
- (supports_clamp ? MALI_WRAP_MODE_CLAMP :
- MALI_WRAP_MODE_CLAMP_TO_BORDER);
+#if PAN_ARCH <= 5
+ MALI_WRAP_MODE_CLAMP;
+#else
+ MALI_WRAP_MODE_CLAMP_TO_BORDER;
+#endif
case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return MALI_WRAP_MODE_CLAMP_TO_EDGE;
case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return MALI_WRAP_MODE_CLAMP_TO_BORDER;
case PIPE_TEX_WRAP_MIRROR_REPEAT: return MALI_WRAP_MODE_MIRRORED_REPEAT;
case PIPE_TEX_WRAP_MIRROR_CLAMP:
return using_nearest ? MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE :
- (supports_clamp ? MALI_WRAP_MODE_MIRRORED_CLAMP :
- MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER);
+#if PAN_ARCH <= 5
+ MALI_WRAP_MODE_MIRRORED_CLAMP;
+#else
+ MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER;
+#endif
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER;
default: unreachable("Invalid wrap");
@@ -279,7 +284,7 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts, mali_ptr *blend_sha
pan_pack(rts + i * pan_size(BLEND), BLEND, cfg) {
cfg.enable = false;
#if PAN_ARCH >= 6
- cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OFF;
+ cfg.internal.mode = MALI_BLEND_MODE_OFF;
#endif
}
@@ -298,14 +303,14 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts, mali_ptr *blend_sha
cfg.round_to_fb_precision = !dithered;
cfg.alpha_to_one = ctx->blend->base.alpha_to_one;
#if PAN_ARCH >= 6
- cfg.bifrost.constant = pack_blend_constant(format, cons);
+ cfg.constant = pack_blend_constant(format, cons);
#else
- cfg.midgard.blend_shader = (blend_shaders[i] != 0);
+ cfg.blend_shader = (blend_shaders[i] != 0);
if (blend_shaders[i])
- cfg.midgard.shader_pc = blend_shaders[i];
+ cfg.shader_pc = blend_shaders[i];
else
- cfg.midgard.constant = cons;
+ cfg.constant = cons;
#endif
}
@@ -333,17 +338,17 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts, mali_ptr *blend_sha
unsigned ret_offset = fs->info.bifrost.blend[i].return_offset;
assert(!(ret_offset & 0x7));
- pan_pack(&packed->opaque[2], BIFROST_INTERNAL_BLEND, cfg) {
- cfg.mode = MALI_BIFROST_BLEND_MODE_SHADER;
+ pan_pack(&packed->opaque[2], INTERNAL_BLEND, cfg) {
+ cfg.mode = MALI_BLEND_MODE_SHADER;
cfg.shader.pc = (u32) blend_shaders[i];
cfg.shader.return_value = ret_offset ?
fs->bin.gpu + ret_offset : 0;
}
} else {
- pan_pack(&packed->opaque[2], BIFROST_INTERNAL_BLEND, cfg) {
+ pan_pack(&packed->opaque[2], INTERNAL_BLEND, cfg) {
cfg.mode = info.opaque ?
- MALI_BIFROST_BLEND_MODE_OPAQUE :
- MALI_BIFROST_BLEND_MODE_FIXED_FUNCTION;
+ MALI_BLEND_MODE_OPAQUE :
+ MALI_BLEND_MODE_FIXED_FUNCTION;
/* If we want the conversion to work properly,
* num_comps must be set to 4
@@ -378,15 +383,15 @@ pan_merge_empty_fs(struct mali_renderer_state_packed *rsd)
pan_pack(&empty_rsd, RENDERER_STATE, cfg) {
#if PAN_ARCH >= 6
- cfg.properties.bifrost.shader_modifies_coverage = true;
- cfg.properties.bifrost.allow_forward_pixel_to_kill = true;
- cfg.properties.bifrost.allow_forward_pixel_to_be_killed = true;
- cfg.properties.bifrost.zs_update_operation = MALI_PIXEL_KILL_STRONG_EARLY;
+ cfg.properties.shader_modifies_coverage = true;
+ cfg.properties.allow_forward_pixel_to_kill = true;
+ cfg.properties.allow_forward_pixel_to_be_killed = true;
+ cfg.properties.zs_update_operation = MALI_PIXEL_KILL_STRONG_EARLY;
#else
cfg.shader.shader = 0x1;
- cfg.properties.midgard.work_register_count = 1;
+ cfg.properties.work_register_count = 1;
cfg.properties.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;
- cfg.properties.midgard.force_early_z = true;
+ cfg.properties.force_early_z = true;
#endif
}
@@ -421,64 +426,64 @@ panfrost_prepare_fs_state(struct panfrost_context *ctx,
uint64_t rt_written = (fs->info.outputs_written >> FRAG_RESULT_DATA0);
bool blend_reads_dest = (so->load_dest_mask & rt_mask);
- cfg.properties.bifrost.allow_forward_pixel_to_kill =
+ cfg.properties.allow_forward_pixel_to_kill =
fs->info.fs.can_fpk &&
!(rt_mask & ~rt_written) &&
!alpha_to_coverage &&
!blend_reads_dest;
#else
- cfg.properties.midgard.force_early_z =
+ cfg.properties.force_early_z =
fs->info.fs.can_early_z && !alpha_to_coverage &&
((enum mali_func) zsa->base.alpha_func == MALI_FUNC_ALWAYS);
/* TODO: Reduce this limit? */
if (has_blend_shader)
- cfg.properties.midgard.work_register_count = MAX2(fs->info.work_reg_count, 8);
+ cfg.properties.work_register_count = MAX2(fs->info.work_reg_count, 8);
else
- cfg.properties.midgard.work_register_count = fs->info.work_reg_count;
+ cfg.properties.work_register_count = fs->info.work_reg_count;
/* Hardware quirks around early-zs forcing without a
* depth buffer. Note this breaks occlusion queries. */
bool has_oq = ctx->occlusion_query && ctx->active_queries;
bool force_ez_with_discard = !zsa->enabled && !has_oq;
- cfg.properties.midgard.shader_reads_tilebuffer =
+ cfg.properties.shader_reads_tilebuffer =
force_ez_with_discard && fs->info.fs.can_discard;
- cfg.properties.midgard.shader_contains_discard =
+ cfg.properties.shader_contains_discard =
!force_ez_with_discard && fs->info.fs.can_discard;
#endif
}
#if PAN_ARCH == 4
if (rt_count > 0) {
- cfg.multisample_misc.sfbd_load_destination = so->info[0].load_dest;
- cfg.multisample_misc.sfbd_blend_shader = (blend_shaders[0] != 0);
- cfg.stencil_mask_misc.sfbd_write_enable = !so->info[0].no_colour;
- cfg.stencil_mask_misc.sfbd_srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format);
- cfg.stencil_mask_misc.sfbd_dither_disable = !so->base.dither;
- cfg.stencil_mask_misc.sfbd_alpha_to_one = so->base.alpha_to_one;
+ cfg.multisample_misc.load_destination = so->info[0].load_dest;
+ cfg.multisample_misc.blend_shader = (blend_shaders[0] != 0);
+ cfg.stencil_mask_misc.write_enable = !so->info[0].no_colour;
+ cfg.stencil_mask_misc.srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format);
+ cfg.stencil_mask_misc.dither_disable = !so->base.dither;
+ cfg.stencil_mask_misc.alpha_to_one = so->base.alpha_to_one;
if (blend_shaders[0]) {
- cfg.sfbd_blend_shader = blend_shaders[0];
+ cfg.blend_shader = blend_shaders[0];
} else {
- cfg.sfbd_blend_constant = pan_blend_get_constant(
+ cfg.blend_constant = pan_blend_get_constant(
so->info[0].constant_mask,
ctx->blend_color.color);
}
} else {
/* If there is no colour buffer, leaving fields default is
* fine, except for blending which is nonnullable */
- cfg.sfbd_blend_equation.color_mask = 0xf;
- cfg.sfbd_blend_equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.sfbd_blend_equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.sfbd_blend_equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.sfbd_blend_equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.sfbd_blend_equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.sfbd_blend_equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
+ cfg.blend_equation.color_mask = 0xf;
+ cfg.blend_equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
+ cfg.blend_equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
+ cfg.blend_equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
+ cfg.blend_equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
+ cfg.blend_equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
+ cfg.blend_equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
}
#elif PAN_ARCH == 5
/* Workaround */
- cfg.sfbd_blend_shader = panfrost_last_nonnull(blend_shaders, rt_count);
+ cfg.legacy_blend_shader = panfrost_last_nonnull(blend_shaders, rt_count);
#endif
cfg.multisample_misc.sample_mask = msaa ? ctx->sample_mask : 0xFFFF;
@@ -921,7 +926,7 @@ panfrost_upload_rt_conversion_sysval(struct panfrost_batch *batch,
uniform->u[0] =
GENX(pan_blend_get_internal_desc)(dev, format, rt, size, false) >> 32;
} else {
- pan_pack(&uniform->u[0], BIFROST_INTERNAL_CONVERSION, cfg)
+ pan_pack(&uniform->u[0], INTERNAL_CONVERSION, cfg)
cfg.memory_format = dev->formats[PIPE_FORMAT_NONE].hw;
}
}
@@ -1324,8 +1329,8 @@ panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so,
void *tex = (PAN_ARCH >= 6) ? &so->bifrost_descriptor : payload.cpu;
if (PAN_ARCH <= 5) {
- payload.cpu += pan_size(MIDGARD_TEXTURE);
- payload.gpu += pan_size(MIDGARD_TEXTURE);
+ payload.cpu += pan_size(TEXTURE);
+ payload.gpu += pan_size(TEXTURE);
}
GENX(panfrost_new_texture)(device, &iview, tex, &payload);
@@ -1356,9 +1361,9 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch,
struct panfrost_ptr T =
pan_pool_alloc_desc_array(&batch->pool.base,
ctx->sampler_view_count[stage],
- BIFROST_TEXTURE);
- struct mali_bifrost_texture_packed *out =
- (struct mali_bifrost_texture_packed *) T.cpu;
+ TEXTURE);
+ struct mali_texture_packed *out =
+ (struct mali_texture_packed *) T.cpu;
for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) {
struct panfrost_sampler_view *view = ctx->sampler_views[stage][i];
@@ -1400,14 +1405,11 @@ panfrost_emit_sampler_descriptors(struct panfrost_batch *batch,
if (!ctx->sampler_count[stage])
return 0;
- assert(pan_size(BIFROST_SAMPLER) == pan_size(MIDGARD_SAMPLER));
- assert(pan_alignment(BIFROST_SAMPLER) == pan_alignment(MIDGARD_SAMPLER));
-
struct panfrost_ptr T =
pan_pool_alloc_desc_array(&batch->pool.base,
ctx->sampler_count[stage],
- MIDGARD_SAMPLER);
- struct mali_midgard_sampler_packed *out = (struct mali_midgard_sampler_packed *) T.cpu;
+ SAMPLER);
+ struct mali_sampler_packed *out = (struct mali_sampler_packed *) T.cpu;
for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i)
out[i] = ctx->samplers[stage][i]->hw;
@@ -2445,8 +2447,10 @@ pan_draw_mode(enum pipe_prim_type mode)
DEFINE_CASE(TRIANGLE_STRIP);
DEFINE_CASE(TRIANGLE_FAN);
DEFINE_CASE(QUADS);
- DEFINE_CASE(QUAD_STRIP);
DEFINE_CASE(POLYGON);
+#if PAN_ARCH <= 6
+ DEFINE_CASE(QUAD_STRIP);
+#endif
default:
unreachable("Invalid draw mode");
@@ -2530,7 +2534,6 @@ panfrost_draw_emit_vertex(struct panfrost_batch *batch,
pan_section_pack(job, COMPUTE_JOB, DRAW, cfg) {
cfg.draw_descriptor_is_64b = true;
- cfg.texture_descriptor_is_64b = (PAN_ARCH <= 5);
cfg.state = batch->rsd[PIPE_SHADER_VERTEX];
cfg.attributes = attribs;
cfg.attribute_buffers = attrib_bufs;
@@ -2539,8 +2542,6 @@ panfrost_draw_emit_vertex(struct panfrost_batch *batch,
cfg.thread_storage = batch->tls.gpu;
pan_emit_draw_descs(batch, &cfg, PIPE_SHADER_VERTEX);
}
-
- pan_section_pack(job, COMPUTE_JOB, DRAW_PADDING, cfg);
}
static void
@@ -2723,14 +2724,12 @@ panfrost_draw_emit_tiler(struct panfrost_batch *batch,
}
pan_section_pack(job, TILER_JOB, PADDING, cfg);
- pan_section_pack(job, TILER_JOB, DRAW_PADDING, cfg);
#endif
section = pan_section_ptr(job, TILER_JOB, DRAW);
pan_pack(section, DRAW, cfg) {
cfg.four_components_per_vertex = true;
cfg.draw_descriptor_is_64b = true;
- cfg.texture_descriptor_is_64b = (PAN_ARCH <= 5);
cfg.front_face_ccw = rast->front_ccw;
cfg.cull_front_face = rast->cull_face & PIPE_FACE_FRONT;
cfg.cull_back_face = rast->cull_face & PIPE_FACE_BACK;
@@ -3160,7 +3159,6 @@ panfrost_launch_grid(struct pipe_context *pipe,
pan_section_pack(t.cpu, COMPUTE_JOB, DRAW, cfg) {
cfg.draw_descriptor_is_64b = true;
- cfg.texture_descriptor_is_64b = (PAN_ARCH <= 5);
cfg.state = panfrost_emit_compute_shader_meta(batch, PIPE_SHADER_COMPUTE);
cfg.attributes = panfrost_emit_image_attribs(batch, &cfg.attribute_buffers, PIPE_SHADER_COMPUTE);
cfg.thread_storage = panfrost_emit_shared_memory(batch, info);
@@ -3172,8 +3170,6 @@ panfrost_launch_grid(struct pipe_context *pipe,
PIPE_SHADER_COMPUTE);
}
- pan_section_pack(t.cpu, COMPUTE_JOB, DRAW_PADDING, cfg);
-
unsigned indirect_dep = 0;
if (info->indirect) {
struct pan_indirect_dispatch_info indirect = {
@@ -3543,10 +3539,10 @@ init_batch(struct panfrost_batch *batch)
/* Reserve the framebuffer and local storage descriptors */
batch->framebuffer =
#if PAN_ARCH == 4
- pan_pool_alloc_desc(&batch->pool.base, SINGLE_TARGET_FRAMEBUFFER);
+ pan_pool_alloc_desc(&batch->pool.base, FRAMEBUFFER);
#else
pan_pool_alloc_desc_aggregate(&batch->pool.base,
- PAN_DESC(MULTI_TARGET_FRAMEBUFFER),
+ PAN_DESC(FRAMEBUFFER),
PAN_DESC(ZS_CRC_EXTENSION),
PAN_DESC_ARRAY(MAX2(batch->key.nr_cbufs, 1), RENDER_TARGET));
diff --git a/src/panfrost/lib/decode.c b/src/panfrost/lib/decode.c
index 9610373ccd4..f9e85efcb3b 100644
--- a/src/panfrost/lib/decode.c
+++ b/src/panfrost/lib/decode.c
@@ -158,14 +158,14 @@ pandecode_validate_buffer(mali_ptr addr, size_t sz)
static void
pandecode_midgard_tiler_descriptor(
- const struct mali_midgard_tiler_packed *tp,
- const struct mali_midgard_tiler_weights_packed *wp)
+ const struct mali_tiler_context_packed *tp,
+ const struct mali_tiler_weights_packed *wp)
{
pan_unpack(tp, TILER_CONTEXT, t);
DUMP_UNPACKED(TILER_CONTEXT, t, "Tiler:\n");
/* We've never seen weights used in practice, but they exist */
- pan_unpack(wp, MIDGARD_TILER_WEIGHTS, w);
+ pan_unpack(wp, TILER_WEIGHTS, w);
bool nonzero_weights = false;
nonzero_weights |= w.weight0 != 0x0;
@@ -178,7 +178,7 @@ pandecode_midgard_tiler_descriptor(
nonzero_weights |= w.weight7 != 0x0;
if (nonzero_weights)
- DUMP_UNPACKED(MIDGARD_TILER_WEIGHTS, w, "Tiler Weights:\n");
+ DUMP_UNPACKED(TILER_WEIGHTS, w, "Tiler Weights:\n");
}
#endif
@@ -192,7 +192,7 @@ struct pandecode_fbd {
bool has_extra;
};
-#if PAN_ARCH <= 5
+#if PAN_ARCH == 4
static struct pandecode_fbd
pandecode_sfbd(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_id)
{
@@ -204,15 +204,15 @@ pandecode_sfbd(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_id)
.rt_count = 1
};
- pandecode_log("Single-Target Framebuffer:\n");
+ pandecode_log("Framebuffer:\n");
pandecode_indent++;
- DUMP_SECTION(SINGLE_TARGET_FRAMEBUFFER, LOCAL_STORAGE, s, "Local Storage:\n");
- pan_section_unpack(s, SINGLE_TARGET_FRAMEBUFFER, PARAMETERS, p);
- DUMP_UNPACKED(SINGLE_TARGET_FRAMEBUFFER_PARAMETERS, p, "Parameters:\n");
+ DUMP_SECTION(FRAMEBUFFER, LOCAL_STORAGE, s, "Local Storage:\n");
+ pan_section_unpack(s, FRAMEBUFFER, PARAMETERS, p);
+ DUMP_UNPACKED(FRAMEBUFFER_PARAMETERS, p, "Parameters:\n");
- const void *t = pan_section_ptr(s, SINGLE_TARGET_FRAMEBUFFER, TILER);
- const void *w = pan_section_ptr(s, SINGLE_TARGET_FRAMEBUFFER, TILER_WEIGHTS);
+ const void *t = pan_section_ptr(s, FRAMEBUFFER, TILER);
+ const void *w = pan_section_ptr(s, FRAMEBUFFER, TILER_WEIGHTS);
pandecode_midgard_tiler_descriptor(t, w);
@@ -221,14 +221,15 @@ pandecode_sfbd(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_id)
/* Dummy unpack of the padding section to make sure all words are 0.
* No need to call print here since the section is supposed to be empty.
*/
- pan_section_unpack(s, SINGLE_TARGET_FRAMEBUFFER, PADDING_1, padding1);
- pan_section_unpack(s, SINGLE_TARGET_FRAMEBUFFER, PADDING_2, padding2);
+ pan_section_unpack(s, FRAMEBUFFER, PADDING_1, padding1);
+ pan_section_unpack(s, FRAMEBUFFER, PADDING_2, padding2);
pandecode_log("\n");
return info;
}
#endif
+#if PAN_ARCH >= 5
static void
pandecode_local_storage(uint64_t gpu_va, int job_no)
{
@@ -239,7 +240,7 @@ pandecode_local_storage(uint64_t gpu_va, int job_no)
static void
pandecode_render_target(uint64_t gpu_va, unsigned job_no, unsigned gpu_id,
- const struct MALI_MULTI_TARGET_FRAMEBUFFER_PARAMETERS *fb)
+ const struct MALI_FRAMEBUFFER_PARAMETERS *fb)
{
pandecode_log("Color Render Targets:\n");
pandecode_indent++;
@@ -255,12 +256,13 @@ pandecode_render_target(uint64_t gpu_va, unsigned job_no, unsigned gpu_id,
pandecode_indent--;
pandecode_log("\n");
}
+#endif
#if PAN_ARCH >= 6
static void
pandecode_sample_locations(const void *fb, int job_no)
{
- pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, BIFROST_PARAMETERS, params);
+ pan_section_unpack(fb, FRAMEBUFFER, PARAMETERS, params);
struct pandecode_mapped_memory *smem =
pandecode_find_mapped_gpu_mem_containing(params.sample_locations);
@@ -281,20 +283,21 @@ pandecode_dcd(const struct MALI_DRAW *p,
int job_no, enum mali_job_type job_type,
char *suffix, unsigned gpu_id);
+#if PAN_ARCH >= 5
static struct pandecode_fbd
pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_id)
{
struct pandecode_mapped_memory *mem = pandecode_find_mapped_gpu_mem_containing(gpu_va);
const void *PANDECODE_PTR_VAR(fb, mem, (mali_ptr) gpu_va);
- pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, PARAMETERS, params);
+ pan_section_unpack(fb, FRAMEBUFFER, PARAMETERS, params);
struct pandecode_fbd info;
#if PAN_ARCH >= 6
pandecode_sample_locations(fb, job_no);
- pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, BIFROST_PARAMETERS, bparams);
- unsigned dcd_size = pan_size(DRAW) + pan_size(DRAW_PADDING);
+ pan_section_unpack(fb, FRAMEBUFFER, PARAMETERS, bparams);
+ unsigned dcd_size = pan_size(DRAW);
struct pandecode_mapped_memory *dcdmem =
pandecode_find_mapped_gpu_mem_containing(bparams.frame_shader_dcds);
@@ -324,27 +327,24 @@ pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_i
pandecode_indent++;
#if PAN_ARCH <= 5
- DUMP_SECTION(MULTI_TARGET_FRAMEBUFFER, LOCAL_STORAGE, fb, "Local Storage:\n");
+ DUMP_SECTION(FRAMEBUFFER, LOCAL_STORAGE, fb, "Local Storage:\n");
#endif
info.width = params.width;
info.height = params.height;
info.rt_count = params.render_target_count;
- DUMP_UNPACKED(MULTI_TARGET_FRAMEBUFFER_PARAMETERS, params, "Parameters:\n");
+ DUMP_UNPACKED(FRAMEBUFFER_PARAMETERS, params, "Parameters:\n");
-#if PAN_ARCH >= 6
- DUMP_SECTION(MULTI_TARGET_FRAMEBUFFER, BIFROST_TILER_POINTER, fb, "Tiler Pointer");
- pan_section_unpack(fb, MULTI_TARGET_FRAMEBUFFER, BIFROST_PADDING, padding);
-#else
- const void *t = pan_section_ptr(fb, MULTI_TARGET_FRAMEBUFFER, TILER);
- const void *w = pan_section_ptr(fb, MULTI_TARGET_FRAMEBUFFER, TILER_WEIGHTS);
+#if PAN_ARCH <= 5
+ const void *t = pan_section_ptr(fb, FRAMEBUFFER, TILER);
+ const void *w = pan_section_ptr(fb, FRAMEBUFFER, TILER_WEIGHTS);
pandecode_midgard_tiler_descriptor(t, w);
#endif
pandecode_indent--;
pandecode_log("\n");
- gpu_va += pan_size(MULTI_TARGET_FRAMEBUFFER);
+ gpu_va += pan_size(FRAMEBUFFER);
info.has_extra = params.has_zs_crc_extension;
@@ -363,6 +363,7 @@ pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_i
return info;
}
+#endif
static void
pandecode_attributes(const struct pandecode_mapped_memory *mem,
@@ -417,18 +418,18 @@ pandecode_bifrost_blend(void *descs, int job_no, int rt_no, mali_ptr frag_shader
{
pan_unpack(descs + (rt_no * pan_size(BLEND)), BLEND, b);
DUMP_UNPACKED(BLEND, b, "Blend RT %d:\n", rt_no);
- if (b.bifrost.internal.mode != MALI_BIFROST_BLEND_MODE_SHADER)
+ if (b.internal.mode != MALI_BLEND_MODE_SHADER)
return 0;
- return (frag_shader & 0xFFFFFFFF00000000ULL) | b.bifrost.internal.shader.pc;
+ return (frag_shader & 0xFFFFFFFF00000000ULL) | b.internal.shader.pc;
}
-#else
+#elif PAN_ARCH == 5
static mali_ptr
pandecode_midgard_blend_mrt(void *descs, int job_no, int rt_no)
{
pan_unpack(descs + (rt_no * pan_size(BLEND)), BLEND, b);
DUMP_UNPACKED(BLEND, b, "Blend RT %d:\n", rt_no);
- return b.midgard.blend_shader ? (b.midgard.shader_pc & ~0xf) : 0;
+ return b.blend_shader ? (b.shader_pc & ~0xf) : 0;
}
#endif
@@ -795,21 +796,25 @@ pandecode_dcd(const struct MALI_DRAW *p,
{
struct pandecode_mapped_memory *attr_mem;
+#if PAN_ARCH >= 5
struct pandecode_fbd fbd_info = {
/* Default for Bifrost */
.rt_count = 1
};
+#endif
#if PAN_ARCH >= 6
pandecode_local_storage(p->thread_storage & ~1, job_no);
-#else
- if (job_type != MALI_JOB_TYPE_TILER)
+#elif PAN_ARCH == 5
+ if (job_type != MALI_JOB_TYPE_TILER) {
pandecode_local_storage(p->thread_storage & ~1, job_no);
- else if (p->fbd & MALI_FBD_TAG_IS_MFBD)
+ } else {
+ assert(p->fbd & MALI_FBD_TAG_IS_MFBD);
fbd_info = pandecode_mfbd_bfr((u64) ((uintptr_t) p->fbd) & ~MALI_FBD_TAG_MASK,
job_no, false, gpu_id);
- else
- fbd_info = pandecode_sfbd((u64) (uintptr_t) p->fbd, job_no, false, gpu_id);
+ }
+#else
+ pandecode_sfbd((u64) (uintptr_t) p->fbd, job_no, false, gpu_id);
#endif
int varying_count = 0, attribute_count = 0, uniform_count = 0, uniform_buffer_count = 0;
@@ -843,14 +848,14 @@ pandecode_dcd(const struct MALI_DRAW *p,
#if PAN_ARCH >= 6
uniform_count = state.preload.uniform_count;
#else
- uniform_count = state.properties.midgard.uniform_count;
+ uniform_count = state.properties.uniform_count;
#endif
#if PAN_ARCH >= 6
DUMP_UNPACKED(PRELOAD, state.preload, "Preload:\n");
-#else
- mali_ptr shader = state.sfbd_blend_shader & ~0xF;
- if (state.multisample_misc.sfbd_blend_shader && shader)
+#elif PAN_ARCH == 4
+ mali_ptr shader = state.blend_shader & ~0xF;
+ if (state.multisample_misc.blend_shader && shader)
pandecode_blend_shader_disassemble(shader, job_no, job_type, gpu_id);
#endif
pandecode_indent--;
@@ -859,6 +864,7 @@ pandecode_dcd(const struct MALI_DRAW *p,
/* MRT blend fields are used whenever MFBD is used, with
* per-RT descriptors */
+#if PAN_ARCH >= 5
if ((job_type == MALI_JOB_TYPE_TILER || job_type == MALI_JOB_TYPE_FRAGMENT) &&
(PAN_ARCH >= 6 || p->thread_storage & MALI_FBD_TAG_IS_MFBD)) {
void* blend_base = ((void *) cl) + pan_size(RENDERER_STATE);
@@ -877,6 +883,7 @@ pandecode_dcd(const struct MALI_DRAW *p,
gpu_id);
}
}
+#endif
} else
pandecode_msg("XXX: missing shader descriptor\n");
@@ -992,33 +999,31 @@ pandecode_indexed_vertex_job(const struct MALI_JOB_HEADER *h,
const struct pandecode_mapped_memory *mem,
mali_ptr job, int job_no, unsigned gpu_id)
{
- struct mali_bifrost_indexed_vertex_job_packed *PANDECODE_PTR_VAR(p, mem, job);
+ struct mali_indexed_vertex_job_packed *PANDECODE_PTR_VAR(p, mem, job);
pandecode_log("Vertex:\n");
- pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, VERTEX_DRAW, vert_draw);
+ pan_section_unpack(p, INDEXED_VERTEX_JOB, VERTEX_DRAW, vert_draw);
pandecode_dcd(&vert_draw, job_no, h->type, "", gpu_id);
DUMP_UNPACKED(DRAW, vert_draw, "Vertex Draw:\n");
pandecode_log("Fragment:\n");
- pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, FRAGMENT_DRAW, frag_draw);
+ pan_section_unpack(p, INDEXED_VERTEX_JOB, FRAGMENT_DRAW, frag_draw);
pandecode_dcd(&frag_draw, job_no, MALI_JOB_TYPE_FRAGMENT, "", gpu_id);
DUMP_UNPACKED(DRAW, frag_draw, "Fragment Draw:\n");
- pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, TILER, tiler_ptr);
+ pan_section_unpack(p, INDEXED_VERTEX_JOB, TILER, tiler_ptr);
pandecode_log("Tiler Job Payload:\n");
pandecode_indent++;
pandecode_bifrost_tiler(tiler_ptr.address, job_no);
pandecode_indent--;
- pandecode_invocation(pan_section_ptr(p, BIFROST_INDEXED_VERTEX_JOB, INVOCATION));
- pandecode_primitive(pan_section_ptr(p, BIFROST_INDEXED_VERTEX_JOB, PRIMITIVE));
+ pandecode_invocation(pan_section_ptr(p, INDEXED_VERTEX_JOB, INVOCATION));
+ pandecode_primitive(pan_section_ptr(p, INDEXED_VERTEX_JOB, PRIMITIVE));
/* TODO: gl_PointSize on Bifrost */
- pandecode_primitive_size(pan_section_ptr(p, BIFROST_INDEXED_VERTEX_JOB, PRIMITIVE_SIZE), true);
+ pandecode_primitive_size(pan_section_ptr(p, INDEXED_VERTEX_JOB, PRIMITIVE_SIZE), true);
- pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, PADDING, padding);
- pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, FRAGMENT_DRAW_PADDING, f_padding);
- pan_section_unpack(p, BIFROST_INDEXED_VERTEX_JOB, VERTEX_DRAW_PADDING, v_padding);
+ pan_section_unpack(p, INDEXED_VERTEX_JOB, PADDING, padding);
}
static void
@@ -1026,7 +1031,7 @@ pandecode_tiler_job_bfr(const struct MALI_JOB_HEADER *h,
const struct pandecode_mapped_memory *mem,
mali_ptr job, int job_no, unsigned gpu_id)
{
- struct mali_bifrost_tiler_job_packed *PANDECODE_PTR_VAR(p, mem, job);
+ struct mali_tiler_job_packed *PANDECODE_PTR_VAR(p, mem, job);
pan_section_unpack(p, TILER_JOB, DRAW, draw);
pan_section_unpack(p, TILER_JOB, TILER, tiler_ptr);
pandecode_dcd(&draw, job_no, h->type, "", gpu_id);
@@ -1051,7 +1056,7 @@ pandecode_tiler_job_mdg(const struct MALI_JOB_HEADER *h,
const struct pandecode_mapped_memory *mem,
mali_ptr job, int job_no, unsigned gpu_id)
{
- struct mali_midgard_tiler_job_packed *PANDECODE_PTR_VAR(p, mem, job);
+ struct mali_tiler_job_packed *PANDECODE_PTR_VAR(p, mem, job);
pan_section_unpack(p, TILER_JOB, DRAW, draw);
pandecode_dcd(&draw, job_no, h->type, "", gpu_id);
@@ -1076,47 +1081,43 @@ pandecode_fragment_job(const struct pandecode_mapped_memory *mem,
struct mali_fragment_job_packed *PANDECODE_PTR_VAR(p, mem, job);
pan_section_unpack(p, FRAGMENT_JOB, PAYLOAD, s);
- bool is_mfbd = s.framebuffer & MALI_FBD_TAG_IS_MFBD;
- if (!is_mfbd && PAN_ARCH >= 6)
- pandecode_msg("XXX: Bifrost fragment must use MFBD\n");
+#if PAN_ARCH == 4
+ pandecode_sfbd(s.framebuffer, job_no, true, gpu_id);
+#else
+ assert(s.framebuffer & MALI_FBD_TAG_IS_MFBD);
struct pandecode_fbd info;
-#if PAN_ARCH >= 6
info = pandecode_mfbd_bfr(s.framebuffer & ~MALI_FBD_TAG_MASK, job_no,
true, gpu_id);
-#else
- if (is_mfbd)
- info = pandecode_mfbd_bfr(s.framebuffer & ~MALI_FBD_TAG_MASK, job_no,
- true, gpu_id);
- else
- info = pandecode_sfbd(s.framebuffer & ~MALI_FBD_TAG_MASK, job_no,
- true, gpu_id);
#endif
+#if PAN_ARCH >= 5
+ unsigned expected_tag = 0;
+
/* Compute the tag for the tagged pointer. This contains the type of
* FBD (MFBD/SFBD), and in the case of an MFBD, information about which
* additional structures follow the MFBD header (an extra payload or
* not, as well as a count of render targets) */
- unsigned expected_tag = is_mfbd ? MALI_FBD_TAG_IS_MFBD : 0;
+ expected_tag = MALI_FBD_TAG_IS_MFBD;
+ if (info.has_extra)
+ expected_tag |= MALI_FBD_TAG_HAS_ZS_RT;
- if (is_mfbd) {
- if (info.has_extra)
- expected_tag |= MALI_FBD_TAG_HAS_ZS_RT;
-
- expected_tag |= (MALI_POSITIVE(info.rt_count) << 2);
- }
+ expected_tag |= MALI_FBD_TAG_IS_MFBD | (MALI_POSITIVE(info.rt_count) << 2);
+#endif
DUMP_UNPACKED(FRAGMENT_JOB_PAYLOAD, s, "Fragment Job Payload:\n");
+#if PAN_ARCH >= 5
/* The FBD is a tagged pointer */
unsigned tag = (s.framebuffer & MALI_FBD_TAG_MASK);
if (tag != expected_tag)
pandecode_msg("XXX: expected FBD tag %X but got %X\n", expected_tag, tag);
+#endif
pandecode_log("\n");
}
diff --git a/src/panfrost/lib/gen_macros.h b/src/panfrost/lib/gen_macros.h
index 4dea1e9a82b..1cd33b6e0ec 100644
--- a/src/panfrost/lib/gen_macros.h
+++ b/src/panfrost/lib/gen_macros.h
@@ -74,38 +74,22 @@ pan_arch(unsigned gpu_id)
/* Base macro defined on the command line. */
#ifndef PAN_ARCH
-/* This will be replaced by a minimal definition header as soon as the
- * per-gen transition is complete.
- */
-# include "midgard_pack.h"
+# include "common_pack.h"
#else
-#if PAN_ARCH >= 6
-#define TILER_JOB BIFROST_TILER_JOB
-#define TEXTURE BIFROST_TEXTURE
-#define SAMPLER BIFROST_SAMPLER
-#define TILER_HEAP BIFROST_TILER_HEAP
-#define TILER_CONTEXT BIFROST_TILER
-#else
-#define TILER_JOB MIDGARD_TILER_JOB
-#define TEXTURE MIDGARD_TEXTURE
-#define SAMPLER MIDGARD_SAMPLER
-#define TILER_CONTEXT MIDGARD_TILER
-#endif
-
/* Suffixing macros */
#if (PAN_ARCH == 4)
# define GENX(X) X##_v4
-# include "midgard_pack.h"
+# include "v4_pack.h"
#elif (PAN_ARCH == 5)
# define GENX(X) X##_v5
-# include "midgard_pack.h"
+# include "v5_pack.h"
#elif (PAN_ARCH == 6)
# define GENX(X) X##_v6
-# include "midgard_pack.h"
+# include "v6_pack.h"
#elif (PAN_ARCH == 7)
# define GENX(X) X##_v7
-# include "midgard_pack.h"
+# include "v7_pack.h"
#else
# error "Need to add suffixing macro for this architecture"
#endif
diff --git a/src/panfrost/lib/gen_pack.py b/src/panfrost/lib/gen_pack.py
index 6f97a1b55ad..bd57ee462f0 100644
--- a/src/panfrost/lib/gen_pack.py
+++ b/src/panfrost/lib/gen_pack.py
@@ -182,7 +182,17 @@ __gen_unpack_padded(const uint8_t *restrict cl, uint32_t start, uint32_t end)
(packed1).opaque[i] |= (packed2).opaque[i]; \
} while(0)
-#define mali_pixel_format_print_v6(fp, format) \\
+/* From presentations, 16x16 tiles externally. Use shift for fast computation
+ * of tile numbers. */
+
+#define MALI_TILE_SHIFT 4
+#define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
+
+"""
+
+v6_format_printer = """
+
+#define mali_pixel_format_print(fp, format) \\
fprintf(fp, "%*sFormat (v6): %s%s%s %s%s%s%s\\n", indent, "", \\
mali_format_as_str((enum mali_format)((format >> 12) & 0xFF)), \\
(format & (1 << 20)) ? " sRGB" : "", \\
@@ -192,20 +202,17 @@ __gen_unpack_padded(const uint8_t *restrict cl, uint32_t start, uint32_t end)
mali_channel_as_str((enum mali_channel)((format >> 6) & 0x7)), \\
mali_channel_as_str((enum mali_channel)((format >> 9) & 0x7)));
-#define mali_pixel_format_print_v7(fp, format) \\
+"""
+
+v7_format_printer = """
+
+#define mali_pixel_format_print(fp, format) \\
fprintf(fp, "%*sFormat (v7): %s%s %s%s\\n", indent, "", \\
mali_format_as_str((enum mali_format)((format >> 12) & 0xFF)), \\
(format & (1 << 20)) ? " sRGB" : "", \\
mali_rgb_component_order_as_str((enum mali_rgb_component_order)(format & ((1 << 12) - 1))), \\
(format & (1 << 21)) ? " XXX BAD BIT" : "");
-
-/* From presentations, 16x16 tiles externally. Use shift for fast computation
- * of tile numbers. */
-
-#define MALI_TILE_SHIFT 4
-#define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
-
"""
def to_alphanum(name):
@@ -654,8 +661,7 @@ class Group(object):
elif field.type == "uint/float":
print(' fprintf(fp, "%*s{}: 0x%X (%f)\\n", indent, "", {}, uif({}));'.format(name, val, val))
elif field.type == "Pixel Format":
- print(' mali_pixel_format_print_v6(fp, {});'.format(val))
- print(' mali_pixel_format_print_v7(fp, {});'.format(val))
+ print(' mali_pixel_format_print(fp, {});'.format(val))
else:
print(' fprintf(fp, "%*s{}: %u\\n", indent, "", {});'.format(name, val))
@@ -683,6 +689,12 @@ class Parser(object):
def start_element(self, name, attrs):
if name == "panxml":
print(pack_header)
+ if "arch" in attrs:
+ arch = int(attrs["arch"])
+ if arch <= 6:
+ print(v6_format_printer)
+ else:
+ print(v7_format_printer)
elif name == "struct":
name = attrs["name"]
self.no_direct_packing = attrs.get("no-direct-packing", False)
diff --git a/src/panfrost/lib/meson.build b/src/panfrost/lib/meson.build
index 40e2cf5e23f..dfc72787a2a 100644
--- a/src/panfrost/lib/meson.build
+++ b/src/panfrost/lib/meson.build
@@ -20,7 +20,7 @@
# SOFTWARE.
pan_packers = []
-foreach packer : ['common', 'midgard']
+foreach packer : ['common', 'v4', 'v5', 'v6', 'v7']
pan_packers += custom_target(
packer + '_pack.h',
input : ['gen_pack.py', packer + '.xml'],
diff --git a/src/panfrost/lib/pan_blend.c b/src/panfrost/lib/pan_blend.c
index a7a204dba27..fdd3aad7651 100644
--- a/src/panfrost/lib/pan_blend.c
+++ b/src/panfrost/lib/pan_blend.c
@@ -23,7 +23,11 @@
*/
#include "pan_blend.h"
+
+#ifdef PAN_ARCH
#include "pan_shader.h"
+#endif
+
#include "pan_texture.h"
#include "panfrost/util/pan_lower_framebuffer.h"
#include "util/format/u_format.h"
@@ -623,8 +627,8 @@ GENX(pan_blend_get_internal_desc)(const struct panfrost_device *dev,
const struct util_format_description *desc = util_format_description(fmt);
uint64_t res;
- pan_pack(&res, BIFROST_INTERNAL_BLEND, cfg) {
- cfg.mode = MALI_BIFROST_BLEND_MODE_OPAQUE;
+ pan_pack(&res, INTERNAL_BLEND, cfg) {
+ cfg.mode = MALI_BLEND_MODE_OPAQUE;
cfg.fixed_function.num_comps = desc->nr_channels;
cfg.fixed_function.rt = rt;
@@ -636,29 +640,29 @@ GENX(pan_blend_get_internal_desc)(const struct panfrost_device *dev,
switch (T) {
case nir_type_float16:
cfg.fixed_function.conversion.register_format =
- MALI_BIFROST_REGISTER_FILE_FORMAT_F16;
+ MALI_REGISTER_FILE_FORMAT_F16;
break;
case nir_type_float32:
cfg.fixed_function.conversion.register_format =
- MALI_BIFROST_REGISTER_FILE_FORMAT_F32;
+ MALI_REGISTER_FILE_FORMAT_F32;
break;
case nir_type_int8:
case nir_type_int16:
cfg.fixed_function.conversion.register_format =
- MALI_BIFROST_REGISTER_FILE_FORMAT_I16;
+ MALI_REGISTER_FILE_FORMAT_I16;
break;
case nir_type_int32:
cfg.fixed_function.conversion.register_format =
- MALI_BIFROST_REGISTER_FILE_FORMAT_I32;
+ MALI_REGISTER_FILE_FORMAT_I32;
break;
case nir_type_uint8:
case nir_type_uint16:
cfg.fixed_function.conversion.register_format =
- MALI_BIFROST_REGISTER_FILE_FORMAT_U16;
+ MALI_REGISTER_FILE_FORMAT_U16;
break;
case nir_type_uint32:
cfg.fixed_function.conversion.register_format =
- MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
+ MALI_REGISTER_FILE_FORMAT_U32;
break;
default:
unreachable("Invalid format");
diff --git a/src/panfrost/lib/pan_blitter.c b/src/panfrost/lib/pan_blitter.c
index 16980bf5cbd..fce7a2c01ef 100644
--- a/src/panfrost/lib/pan_blitter.c
+++ b/src/panfrost/lib/pan_blitter.c
@@ -48,16 +48,16 @@
* This is primarily designed as a fallback for preloads but could be extended
* for other clears/blits if needed in the future. */
-static enum mali_bifrost_register_file_format
+static enum mali_register_file_format
blit_type_to_reg_fmt(nir_alu_type in)
{
switch (in) {
case nir_type_float32:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_F32;
+ return MALI_REGISTER_FILE_FORMAT_F32;
case nir_type_int32:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_I32;
+ return MALI_REGISTER_FILE_FORMAT_I32;
case nir_type_uint32:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
+ return MALI_REGISTER_FILE_FORMAT_U32;
default:
unreachable("Invalid blit type");
}
@@ -126,7 +126,7 @@ pan_blitter_emit_blend(const struct panfrost_device *dev,
if (!iview) {
cfg.enable = false;
#if PAN_ARCH >= 6
- cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OFF;
+ cfg.internal.mode = MALI_BLEND_MODE_OFF;
#endif
continue;
}
@@ -135,49 +135,42 @@ pan_blitter_emit_blend(const struct panfrost_device *dev,
cfg.srgb = util_format_is_srgb(iview->format);
#if PAN_ARCH >= 6
- cfg.bifrost.internal.mode = blend_shader ?
- MALI_BIFROST_BLEND_MODE_SHADER :
- MALI_BIFROST_BLEND_MODE_OPAQUE;
+ cfg.internal.mode = blend_shader ?
+ MALI_BLEND_MODE_SHADER :
+ MALI_BLEND_MODE_OPAQUE;
#endif
if (!blend_shader) {
+ cfg.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
+ cfg.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
+ cfg.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
+ cfg.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
+ cfg.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
+ cfg.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
+ cfg.equation.color_mask = 0xf;
+
#if PAN_ARCH >= 6
nir_alu_type type = blit_shader->key.surfaces[rt].type;
- cfg.bifrost.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.bifrost.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.bifrost.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.bifrost.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.bifrost.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.bifrost.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.bifrost.equation.color_mask = 0xf;
- cfg.bifrost.internal.fixed_function.num_comps = 4;
- cfg.bifrost.internal.fixed_function.conversion.memory_format =
+ cfg.internal.fixed_function.num_comps = 4;
+ cfg.internal.fixed_function.conversion.memory_format =
panfrost_format_to_bifrost_blend(dev, iview->format, false);
- cfg.bifrost.internal.fixed_function.conversion.register_format =
+ cfg.internal.fixed_function.conversion.register_format =
blit_type_to_reg_fmt(type);
- cfg.bifrost.internal.fixed_function.rt = rt;
-#else
- cfg.midgard.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.midgard.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.midgard.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.midgard.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.midgard.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.midgard.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.midgard.equation.color_mask = 0xf;
+ cfg.internal.fixed_function.rt = rt;
#endif
} else {
#if PAN_ARCH >= 6
- cfg.bifrost.internal.shader.pc = blend_shader;
+ cfg.internal.shader.pc = blend_shader;
if (blit_shader->blend_ret_offsets[rt]) {
- cfg.bifrost.internal.shader.return_value =
+ cfg.internal.shader.return_value =
blit_shader->address +
blit_shader->blend_ret_offsets[rt];
}
#else
- cfg.midgard.blend_shader = true;
- cfg.midgard.shader_pc = blend_shader;
+ cfg.blend_shader = true;
+ cfg.shader_pc = blend_shader;
#endif
}
}
@@ -249,14 +242,14 @@ pan_blitter_emit_rsd(const struct panfrost_device *dev,
#if PAN_ARCH >= 6
if (zs) {
- cfg.properties.bifrost.zs_update_operation =
+ cfg.properties.zs_update_operation =
MALI_PIXEL_KILL_FORCE_LATE;
- cfg.properties.bifrost.pixel_kill_operation =
+ cfg.properties.pixel_kill_operation =
MALI_PIXEL_KILL_FORCE_LATE;
} else {
- cfg.properties.bifrost.zs_update_operation =
+ cfg.properties.zs_update_operation =
MALI_PIXEL_KILL_STRONG_EARLY;
- cfg.properties.bifrost.pixel_kill_operation =
+ cfg.properties.pixel_kill_operation =
MALI_PIXEL_KILL_FORCE_EARLY;
}
@@ -268,8 +261,8 @@ pan_blitter_emit_rsd(const struct panfrost_device *dev,
* for frame shaders it can cause GPU timeouts, so only allow colour
* blit shaders to be killed. */
- cfg.properties.bifrost.allow_forward_pixel_to_kill = !zs;
- cfg.properties.bifrost.allow_forward_pixel_to_be_killed = (dev->arch >= 7) || !zs;
+ cfg.properties.allow_forward_pixel_to_kill = !zs;
+ cfg.properties.allow_forward_pixel_to_be_killed = (dev->arch >= 7) || !zs;
cfg.preload.fragment.coverage = true;
cfg.preload.fragment.sample_mask_id = ms;
@@ -277,30 +270,32 @@ pan_blitter_emit_rsd(const struct panfrost_device *dev,
mali_ptr blend_shader = blend_shaders ?
panfrost_last_nonnull(blend_shaders, rt_count) : 0;
- cfg.properties.midgard.work_register_count = 4;
- cfg.properties.midgard.force_early_z = !zs;
+ cfg.properties.work_register_count = 4;
+ cfg.properties.force_early_z = !zs;
cfg.stencil_mask_misc.alpha_test_compare_function = MALI_FUNC_ALWAYS;
/* Set even on v5 for erratum workaround */
- cfg.sfbd_blend_shader = blend_shader;
-#if PAN_ARCH == 4
- cfg.stencil_mask_misc.sfbd_write_enable = true;
- cfg.stencil_mask_misc.sfbd_dither_disable = true;
- cfg.multisample_misc.sfbd_blend_shader = !!blend_shader;
- cfg.sfbd_blend_shader = blend_shader;
- if (!cfg.multisample_misc.sfbd_blend_shader) {
- cfg.sfbd_blend_equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.sfbd_blend_equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.sfbd_blend_equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.sfbd_blend_equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.sfbd_blend_equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.sfbd_blend_equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.sfbd_blend_constant = 0;
+#if PAN_ARCH == 5
+ cfg.legacy_blend_shader = blend_shader;
+#else
+ cfg.blend_shader = blend_shader;
+ cfg.stencil_mask_misc.write_enable = true;
+ cfg.stencil_mask_misc.dither_disable = true;
+ cfg.multisample_misc.blend_shader = !!blend_shader;
+ cfg.blend_shader = blend_shader;
+ if (!cfg.multisample_misc.blend_shader) {
+ cfg.blend_equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
+ cfg.blend_equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
+ cfg.blend_equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
+ cfg.blend_equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
+ cfg.blend_equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
+ cfg.blend_equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
+ cfg.blend_constant = 0;
if (rts && rts[0]) {
- cfg.stencil_mask_misc.sfbd_srgb =
+ cfg.stencil_mask_misc.srgb =
util_format_is_srgb(rts[0]->format);
- cfg.sfbd_blend_equation.color_mask = 0xf;
+ cfg.blend_equation.color_mask = 0xf;
}
}
#endif
@@ -1007,7 +1002,6 @@ pan_preload_emit_dcd(struct pan_pool *pool,
pan_preload_emit_textures(pool, fb, zs, &cfg);
cfg.samplers = pan_blitter_emit_sampler(pool, true);
- cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
#if PAN_ARCH >= 6
/* Tiles updated by blit shaders are still considered
@@ -1034,7 +1028,6 @@ pan_blit_emit_dcd(struct pan_pool *pool,
cfg.position = dst_coords;
pan_blitter_emit_varying(pool, src_coords, &cfg);
cfg.viewport = vpd;
- cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
cfg.textures = textures;
cfg.samplers = samplers;
}
@@ -1093,13 +1086,7 @@ pan_preload_fb_alloc_pre_post_dcds(struct pan_pool *desc_pool,
return;
fb->bifrost.pre_post.dcds =
- pan_pool_alloc_desc_aggregate(desc_pool,
- PAN_DESC(DRAW),
- PAN_DESC(DRAW_PADDING),
- PAN_DESC(DRAW),
- PAN_DESC(DRAW_PADDING),
- PAN_DESC(DRAW),
- PAN_DESC(DRAW_PADDING));
+ pan_pool_alloc_desc_array(desc_pool, 3, DRAW);
}
static void
@@ -1112,7 +1099,7 @@ pan_preload_emit_pre_frame_dcd(struct pan_pool *desc_pool,
pan_preload_fb_alloc_pre_post_dcds(desc_pool, fb);
assert(fb->bifrost.pre_post.dcds.cpu);
void *dcd = fb->bifrost.pre_post.dcds.cpu +
- (dcd_idx * (pan_size(DRAW) + pan_size(DRAW_PADDING)));
+ (dcd_idx * pan_size(DRAW));
int crc_rt = GENX(pan_select_crc_rt)(fb);
diff --git a/src/panfrost/lib/pan_cs.c b/src/panfrost/lib/pan_cs.c
index 709f2a47693..c5ae5460025 100644
--- a/src/panfrost/lib/pan_cs.c
+++ b/src/panfrost/lib/pan_cs.c
@@ -38,14 +38,14 @@ mod_to_block_fmt(uint64_t mod)
{
switch (mod) {
case DRM_FORMAT_MOD_LINEAR:
- return PAN_ARCH >= 7 ?
- MALI_BLOCK_FORMAT_V7_LINEAR : MALI_BLOCK_FORMAT_LINEAR;
+ return MALI_BLOCK_FORMAT_LINEAR;
case DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED:
- return PAN_ARCH >= 7 ?
- MALI_BLOCK_FORMAT_V7_TILED_U_INTERLEAVED : MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
+ return MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
default:
+#if PAN_ARCH >= 5
if (drm_is_afbc(mod))
- return PAN_ARCH >= 7 ? MALI_BLOCK_FORMAT_V7_AFBC : MALI_BLOCK_FORMAT_AFBC;
+ return MALI_BLOCK_FORMAT_AFBC;
+#endif
unreachable("Unsupported modifer");
}
@@ -164,11 +164,7 @@ pan_prepare_s(const struct pan_fb_info *fb,
unsigned level = s->first_level;
-#if PAN_ARCH <= 6
ext->s_msaa = mali_sampling_mode(s);
-#else
- ext->s_msaa_v7 = mali_sampling_mode(s);
-#endif
struct pan_surface surf;
pan_iview_get_surface(s, 0, 0, 0, &surf);
@@ -180,13 +176,7 @@ pan_prepare_s(const struct pan_fb_info *fb,
ext->s_writeback_surface_stride =
(s->image->layout.nr_samples > 1) ?
s->image->layout.slices[level].surface_stride : 0;
-
-#if PAN_ARCH <= 6
ext->s_block_format = mod_to_block_fmt(s->image->layout.modifier);
-#else
- ext->s_block_format_v7 = mod_to_block_fmt(s->image->layout.modifier);
-#endif
-
ext->s_write_format = translate_s_format(s->format);
}
@@ -201,11 +191,7 @@ pan_prepare_zs(const struct pan_fb_info *fb,
unsigned level = zs->first_level;
-#if PAN_ARCH <= 6
ext->zs_msaa = mali_sampling_mode(zs);
-#else
- ext->zs_msaa_v7 = mali_sampling_mode(zs);
-#endif
struct pan_surface surf;
pan_iview_get_surface(zs, 0, 0, 0, &surf);
@@ -239,12 +225,7 @@ pan_prepare_zs(const struct pan_fb_info *fb,
zs->image->layout.slices[level].surface_stride : 0;
}
-#if PAN_ARCH <= 6
ext->zs_block_format = mod_to_block_fmt(zs->image->layout.modifier);
-#else
- ext->zs_block_format_v7 = mod_to_block_fmt(zs->image->layout.modifier);
-#endif
-
ext->zs_write_format = translate_zs_format(zs->format);
if (ext->zs_write_format == MALI_ZS_FORMAT_D24S8)
ext->s_writeback_base = ext->zs_writeback_base;
@@ -269,13 +250,13 @@ pan_prepare_crc(const struct pan_fb_info *fb, int rt_crc,
#if PAN_ARCH >= 7
ext->crc_render_target = rt_crc;
-#endif
if (fb->rts[rt_crc].clear) {
uint32_t clear_val = fb->rts[rt_crc].clear_value[0];
ext->crc_clear_color = clear_val | 0xc000000000000000 |
(((uint64_t)clear_val & 0xffff) << 32);
}
+#endif
}
static void
@@ -338,26 +319,26 @@ pan_internal_cbuf_size(const struct pan_fb_info *fb,
return total_size;
}
-static enum mali_mfbd_color_format
+static enum mali_color_format
pan_mfbd_raw_format(unsigned bits)
{
switch (bits) {
- case 8: return MALI_MFBD_COLOR_FORMAT_RAW8;
- case 16: return MALI_MFBD_COLOR_FORMAT_RAW16;
- case 24: return MALI_MFBD_COLOR_FORMAT_RAW24;
- case 32: return MALI_MFBD_COLOR_FORMAT_RAW32;
- case 48: return MALI_MFBD_COLOR_FORMAT_RAW48;
- case 64: return MALI_MFBD_COLOR_FORMAT_RAW64;
- case 96: return MALI_MFBD_COLOR_FORMAT_RAW96;
- case 128: return MALI_MFBD_COLOR_FORMAT_RAW128;
- case 192: return MALI_MFBD_COLOR_FORMAT_RAW192;
- case 256: return MALI_MFBD_COLOR_FORMAT_RAW256;
- case 384: return MALI_MFBD_COLOR_FORMAT_RAW384;
- case 512: return MALI_MFBD_COLOR_FORMAT_RAW512;
- case 768: return MALI_MFBD_COLOR_FORMAT_RAW768;
- case 1024: return MALI_MFBD_COLOR_FORMAT_RAW1024;
- case 1536: return MALI_MFBD_COLOR_FORMAT_RAW1536;
- case 2048: return MALI_MFBD_COLOR_FORMAT_RAW2048;
+ case 8: return MALI_COLOR_FORMAT_RAW8;
+ case 16: return MALI_COLOR_FORMAT_RAW16;
+ case 24: return MALI_COLOR_FORMAT_RAW24;
+ case 32: return MALI_COLOR_FORMAT_RAW32;
+ case 48: return MALI_COLOR_FORMAT_RAW48;
+ case 64: return MALI_COLOR_FORMAT_RAW64;
+ case 96: return MALI_COLOR_FORMAT_RAW96;
+ case 128: return MALI_COLOR_FORMAT_RAW128;
+ case 192: return MALI_COLOR_FORMAT_RAW192;
+ case 256: return MALI_COLOR_FORMAT_RAW256;
+ case 384: return MALI_COLOR_FORMAT_RAW384;
+ case 512: return MALI_COLOR_FORMAT_RAW512;
+ case 768: return MALI_COLOR_FORMAT_RAW768;
+ case 1024: return MALI_COLOR_FORMAT_RAW1024;
+ case 1536: return MALI_COLOR_FORMAT_RAW1536;
+ case 2048: return MALI_COLOR_FORMAT_RAW2048;
default: unreachable("invalid raw bpp");
}
}
@@ -425,7 +406,7 @@ pan_prepare_rt(const struct pan_fb_info *fb, unsigned idx,
cfg->internal_format = MALI_COLOR_BUFFER_INTERNAL_FORMAT_R8G8B8A8;
cfg->internal_buffer_offset = cbuf_offset;
#if PAN_ARCH >= 7
- cfg->bifrost_v7.writeback_block_format = MALI_BLOCK_FORMAT_V7_TILED_U_INTERLEAVED;
+ cfg->writeback_block_format = MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
cfg->dithering_enable = true;
#endif
return;
@@ -450,10 +431,10 @@ pan_prepare_rt(const struct pan_fb_info *fb, unsigned idx,
pan_rt_init_format(rt, cfg);
-#if PAN_ARCH <= 6
- cfg->midgard.writeback_block_format = mod_to_block_fmt(rt->image->layout.modifier);
+#if PAN_ARCH <= 5
+ cfg->writeback_block_format = mod_to_block_fmt(rt->image->layout.modifier);
#else
- cfg->bifrost_v7.writeback_block_format = mod_to_block_fmt(rt->image->layout.modifier);
+ cfg->writeback_block_format = mod_to_block_fmt(rt->image->layout.modifier);
#endif
struct pan_surface surf;
@@ -465,11 +446,11 @@ pan_prepare_rt(const struct pan_fb_info *fb, unsigned idx,
#if PAN_ARCH >= 6
cfg->afbc.row_stride = slice->afbc.row_stride /
AFBC_HEADER_BYTES_PER_TILE;
- cfg->bifrost_afbc.afbc_wide_block_enable =
+ cfg->afbc.afbc_wide_block_enable =
panfrost_block_dim(rt->image->layout.modifier, true, 0) > 16;
#else
cfg->afbc.chunk_size = 9;
- cfg->midgard_afbc.sparse = true;
+ cfg->afbc.sparse = true;
cfg->afbc.body_size = slice->afbc.body_size;
#endif
@@ -525,7 +506,7 @@ pan_emit_midgard_tiler(const struct panfrost_device *dev,
assert(tiler_ctx->midgard.polygon_list->ptr.gpu);
- pan_pack(out, MIDGARD_TILER, cfg) {
+ pan_pack(out, TILER_CONTEXT, cfg) {
unsigned header_size;
if (tiler_ctx->midgard.disable) {
@@ -579,21 +560,11 @@ pan_emit_mfbd(const struct panfrost_device *dev,
{
unsigned tags = MALI_FBD_TAG_IS_MFBD;
void *fbd = out;
- void *rtd = out + pan_size(MULTI_TARGET_FRAMEBUFFER);
+ void *rtd = out + pan_size(FRAMEBUFFER);
-#if PAN_ARCH >= 6
- pan_section_pack(fbd, MULTI_TARGET_FRAMEBUFFER, BIFROST_PARAMETERS, params) {
- params.sample_locations =
- panfrost_sample_positions(dev, pan_sample_pattern(fb->nr_samples));
- params.pre_frame_0 = fb->bifrost.pre_post.modes[0];
- params.pre_frame_1 = fb->bifrost.pre_post.modes[1];
- params.post_frame = fb->bifrost.pre_post.modes[2];
- params.frame_shader_dcds = fb->bifrost.pre_post.dcds.gpu;
- }
-#else
+#if PAN_ARCH <= 5
GENX(pan_emit_tls)(tls,
- pan_section_ptr(fbd, MULTI_TARGET_FRAMEBUFFER,
- LOCAL_STORAGE));
+ pan_section_ptr(fbd, FRAMEBUFFER, LOCAL_STORAGE));
#endif
unsigned tile_size;
@@ -601,7 +572,16 @@ pan_emit_mfbd(const struct panfrost_device *dev,
int crc_rt = GENX(pan_select_crc_rt)(fb);
bool has_zs_crc_ext = pan_fbd_has_zs_crc_ext(fb);
- pan_section_pack(fbd, MULTI_TARGET_FRAMEBUFFER, PARAMETERS, cfg) {
+ pan_section_pack(fbd, FRAMEBUFFER, PARAMETERS, cfg) {
+#if PAN_ARCH >= 6
+ cfg.sample_locations =
+ panfrost_sample_positions(dev, pan_sample_pattern(fb->nr_samples));
+ cfg.pre_frame_0 = fb->bifrost.pre_post.modes[0];
+ cfg.pre_frame_1 = fb->bifrost.pre_post.modes[1];
+ cfg.post_frame = fb->bifrost.pre_post.modes[2];
+ cfg.frame_shader_dcds = fb->bifrost.pre_post.dcds.gpu;
+ cfg.tiler = tiler_ctx->bifrost;
+#endif
cfg.width = fb->width;
cfg.height = fb->height;
cfg.bound_max_x = fb->width - 1;
@@ -644,21 +624,18 @@ pan_emit_mfbd(const struct panfrost_device *dev,
}
#if PAN_ARCH >= 6
- pan_section_pack(fbd, MULTI_TARGET_FRAMEBUFFER, BIFROST_TILER_POINTER, cfg) {
- cfg.address = tiler_ctx->bifrost;
- }
- pan_section_pack(fbd, MULTI_TARGET_FRAMEBUFFER, BIFROST_PADDING, padding);
+ pan_section_pack(fbd, FRAMEBUFFER, PADDING, padding);
#else
pan_emit_midgard_tiler(dev, fb, tiler_ctx,
- pan_section_ptr(fbd, MULTI_TARGET_FRAMEBUFFER, TILER));
+ pan_section_ptr(fbd, FRAMEBUFFER, TILER));
/* All weights set to 0, nothing to do here */
- pan_section_pack(fbd, MULTI_TARGET_FRAMEBUFFER, TILER_WEIGHTS, w);
+ pan_section_pack(fbd, FRAMEBUFFER, TILER_WEIGHTS, w);
#endif
if (has_zs_crc_ext) {
pan_emit_zs_crc_ext(fb, crc_rt,
- out + pan_size(MULTI_TARGET_FRAMEBUFFER));
+ out + pan_size(FRAMEBUFFER));
rtd += pan_size(ZS_CRC_EXTENSION);
tags |= MALI_FBD_TAG_HAS_ZS_RT;
}
@@ -689,11 +666,11 @@ pan_emit_sfbd_tiler(const struct panfrost_device *dev,
void *fbd)
{
pan_emit_midgard_tiler(dev, fb, ctx,
- pan_section_ptr(fbd, SINGLE_TARGET_FRAMEBUFFER, TILER));
+ pan_section_ptr(fbd, FRAMEBUFFER, TILER));
/* All weights set to 0, nothing to do here */
- pan_section_pack(fbd, SINGLE_TARGET_FRAMEBUFFER, PADDING_1, padding);
- pan_section_pack(fbd, SINGLE_TARGET_FRAMEBUFFER, TILER_WEIGHTS, w);
+ pan_section_pack(fbd, FRAMEBUFFER, PADDING_1, padding);
+ pan_section_pack(fbd, FRAMEBUFFER, TILER_WEIGHTS, w);
}
static void
@@ -704,9 +681,9 @@ pan_emit_sfbd(const struct panfrost_device *dev,
void *fbd)
{
GENX(pan_emit_tls)(tls,
- pan_section_ptr(fbd, SINGLE_TARGET_FRAMEBUFFER,
+ pan_section_ptr(fbd, FRAMEBUFFER,
LOCAL_STORAGE));
- pan_section_pack(fbd, SINGLE_TARGET_FRAMEBUFFER, PARAMETERS, cfg) {
+ pan_section_pack(fbd, FRAMEBUFFER, PARAMETERS, cfg) {
cfg.bound_max_x = fb->width - 1;
cfg.bound_max_y = fb->height - 1;
cfg.dithering_enable = true;
@@ -799,7 +776,7 @@ pan_emit_sfbd(const struct panfrost_device *dev,
cfg.msaa = mali_sampling_mode(fb->rts[0].view);
}
pan_emit_sfbd_tiler(dev, fb, tiler_ctx, fbd);
- pan_section_pack(fbd, SINGLE_TARGET_FRAMEBUFFER, PADDING_2, padding);
+ pan_section_pack(fbd, FRAMEBUFFER, PADDING_2, padding);
}
#endif
@@ -824,7 +801,7 @@ void
GENX(pan_emit_tiler_heap)(const struct panfrost_device *dev,
void *out)
{
- pan_pack(out, BIFROST_TILER_HEAP, heap) {
+ pan_pack(out, TILER_HEAP, heap) {
heap.size = dev->tiler_heap->size;
heap.base = dev->tiler_heap->ptr.gpu;
heap.bottom = dev->tiler_heap->ptr.gpu;
@@ -842,7 +819,7 @@ GENX(pan_emit_tiler_ctx)(const struct panfrost_device *dev,
unsigned max_levels = dev->tiler_features.max_levels;
assert(max_levels >= 2);
- pan_pack(out, BIFROST_TILER, tiler) {
+ pan_pack(out, TILER_CONTEXT, tiler) {
/* TODO: Select hierarchy mask more effectively */
tiler.hierarchy_mask = (max_levels >= 8) ? 0xFF : 0x28;
tiler.fb_width = fb_width;
@@ -870,10 +847,12 @@ GENX(pan_emit_fragment_job)(const struct pan_fb_info *fb,
payload.bound_max_y = fb->extent.maxy >> MALI_TILE_SHIFT;
payload.framebuffer = fbd;
+#if PAN_ARCH >= 5
if (fb->tile_map.base) {
payload.has_tile_enable_map = true;
payload.tile_enable_map = fb->tile_map.base;
payload.tile_enable_map_row_stride = fb->tile_map.stride;
}
+#endif
}
}
diff --git a/src/panfrost/lib/pan_encoder.h b/src/panfrost/lib/pan_encoder.h
index 1b80f3fc695..fbf7c4d2c53 100644
--- a/src/panfrost/lib/pan_encoder.h
+++ b/src/panfrost/lib/pan_encoder.h
@@ -233,6 +233,7 @@ panfrost_pack_work_groups_compute(
}
}
+#if PAN_ARCH >= 5
/* Format conversion */
static inline enum mali_z_internal_format
panfrost_get_z_internal_format(enum pipe_format fmt)
@@ -251,6 +252,7 @@ panfrost_get_z_internal_format(enum pipe_format fmt)
unreachable("Unsupported depth/stencil format.");
}
}
+#endif
#endif /* PAN_ARCH */
diff --git a/src/panfrost/lib/pan_format.c b/src/panfrost/lib/pan_format.c
index d4cc3817e0d..fe0ec2ab411 100644
--- a/src/panfrost/lib/pan_format.c
+++ b/src/panfrost/lib/pan_format.c
@@ -47,7 +47,7 @@
#define BFMT2(pipe, internal, writeback, srgb) \
[PIPE_FORMAT_##pipe] = { \
MALI_COLOR_BUFFER_INTERNAL_FORMAT_## internal, \
- MALI_MFBD_COLOR_FORMAT_## writeback, \
+ MALI_COLOR_FORMAT_## writeback, \
{ MALI_BLEND_PU_ ## internal | (srgb ? (1 << 20) : 0) | \
PAN_V6_SWIZZLE(R, G, B, A), \
MALI_BLEND_AU_ ## internal | (srgb ? (1 << 20) : 0) | \
@@ -57,7 +57,7 @@
#define BFMT2(pipe, internal, writeback, srgb) \
[PIPE_FORMAT_##pipe] = { \
MALI_COLOR_BUFFER_INTERNAL_FORMAT_## internal, \
- MALI_MFBD_COLOR_FORMAT_## writeback, \
+ MALI_COLOR_FORMAT_## writeback, \
{ MALI_BLEND_PU_ ## internal | (srgb ? (1 << 20) : 0), \
MALI_BLEND_AU_ ## internal | (srgb ? (1 << 20) : 0) } \
}
@@ -439,13 +439,13 @@ const struct panfrost_format GENX(panfrost_pipe_format)[PIPE_FORMAT_COUNT] = {
FMT(A16_FLOAT, R16F, 000R, L, VTR_),
#else
- FMT(Z16_UNORM, RGB332_UNORM /* XXX: Deduplicate enum */, RGBA, L, _T_Z),
+ FMT(Z16_UNORM, Z16_UNORM, RGBA, L, _T_Z),
FMT(Z24_UNORM_S8_UINT, Z24X8_UNORM, RGBA, L, _T_Z),
FMT(Z24X8_UNORM, Z24X8_UNORM, RGBA, L, _T_Z),
FMT(Z32_FLOAT, R32F, RGBA, L, _T_Z),
FMT(Z32_FLOAT_S8X24_UINT, Z32_X32, RGBA, L, _T_Z),
- FMT(X32_S8X24_UINT, X32_S8X24, GRBA, L, _T_Z),
- FMT(X24S8_UINT, TILEBUFFER_NATIVE /* XXX: Deduplicate enum */, GRBA, L, _T_Z),
+ FMT(X32_S8X24_UINT, X32_S8X24, GRBA, L, _T__),
+ FMT(X24S8_UINT, X24S8, GRBA, L, _T_Z),
FMT(S8_UINT, S8, GRBA, L, _T__),
FMT(A8_UNORM, A8_UNORM, 000A, L, VTR_),
diff --git a/src/panfrost/lib/pan_indirect_dispatch.c b/src/panfrost/lib/pan_indirect_dispatch.c
index 0f013db95a0..4c33ae16d49 100644
--- a/src/panfrost/lib/pan_indirect_dispatch.c
+++ b/src/panfrost/lib/pan_indirect_dispatch.c
@@ -141,15 +141,12 @@ GENX(pan_indirect_dispatch_emit)(struct pan_pool *pool,
pan_section_pack(job.cpu, COMPUTE_JOB, DRAW, cfg) {
cfg.draw_descriptor_is_64b = true;
- cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
cfg.state = get_rsd(dev);
cfg.thread_storage = get_tls(pool->dev);
cfg.uniform_buffers = get_ubos(pool, &inputs);
cfg.push_uniforms = get_push_uniforms(pool, &inputs);
}
- pan_section_pack(job.cpu, COMPUTE_JOB, DRAW_PADDING, cfg);
-
return panfrost_add_job(pool, scoreboard, MALI_JOB_TYPE_COMPUTE,
false, true, 0, 0, &job, false);
}
diff --git a/src/panfrost/lib/pan_indirect_draw.c b/src/panfrost/lib/pan_indirect_draw.c
index c2427463e51..f2b73fb5c19 100644
--- a/src/panfrost/lib/pan_indirect_draw.c
+++ b/src/panfrost/lib/pan_indirect_draw.c
@@ -1277,15 +1277,12 @@ panfrost_emit_index_min_max_search(struct pan_pool *pool,
pan_section_pack(job.cpu, COMPUTE_JOB, DRAW, cfg) {
cfg.draw_descriptor_is_64b = true;
- cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
cfg.state = rsd;
cfg.thread_storage = get_tls(pool->dev);
cfg.uniform_buffers = ubos;
cfg.push_uniforms = get_push_uniforms(pool, shader, inputs);
}
- pan_section_pack(job.cpu, COMPUTE_JOB, DRAW_PADDING, cfg);
-
return panfrost_add_job(pool, scoreboard, MALI_JOB_TYPE_COMPUTE,
false, false, 0, 0, &job, false);
}
@@ -1369,15 +1366,12 @@ GENX(panfrost_emit_indirect_draw)(struct pan_pool *pool,
pan_section_pack(job.cpu, COMPUTE_JOB, DRAW, cfg) {
cfg.draw_descriptor_is_64b = true;
- cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
cfg.state = rsd;
cfg.thread_storage = get_tls(pool->dev);
cfg.uniform_buffers = ubos;
cfg.push_uniforms = get_push_uniforms(pool, shader, &inputs);
}
- pan_section_pack(job.cpu, COMPUTE_JOB, DRAW_PADDING, cfg);
-
unsigned global_dep = draw_info->last_indirect_draw;
unsigned local_dep =
panfrost_emit_index_min_max_search(pool, scoreboard, draw_info,
diff --git a/src/panfrost/lib/pan_shader.c b/src/panfrost/lib/pan_shader.c
index aac31457b42..a0243404dc9 100644
--- a/src/panfrost/lib/pan_shader.c
+++ b/src/panfrost/lib/pan_shader.c
@@ -151,24 +151,24 @@ collect_varyings(nir_shader *s, nir_variable_mode varying_mode,
}
#if PAN_ARCH >= 6
-static enum mali_bifrost_register_file_format
+static enum mali_register_file_format
bifrost_blend_type_from_nir(nir_alu_type nir_type)
{
switch(nir_type) {
case 0: /* Render target not in use */
return 0;
case nir_type_float16:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_F16;
+ return MALI_REGISTER_FILE_FORMAT_F16;
case nir_type_float32:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_F32;
+ return MALI_REGISTER_FILE_FORMAT_F32;
case nir_type_int32:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_I32;
+ return MALI_REGISTER_FILE_FORMAT_I32;
case nir_type_uint32:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
+ return MALI_REGISTER_FILE_FORMAT_U32;
case nir_type_int16:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_I16;
+ return MALI_REGISTER_FILE_FORMAT_I16;
case nir_type_uint16:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_U16;
+ return MALI_REGISTER_FILE_FORMAT_U16;
default:
unreachable("Unsupported blend shader type for NIR alu type");
return 0;
@@ -191,7 +191,7 @@ GENX(pan_shader_compile)(nir_shader *s,
enum pipe_format fmt = inputs->rt_formats[i];
unsigned wb_fmt = panfrost_blendable_formats_v6[fmt].writeback;
- if (wb_fmt <= MALI_MFBD_COLOR_FORMAT_RAW2048)
+ if (wb_fmt < MALI_COLOR_FORMAT_R8)
inputs->raw_fmt_mask |= BITFIELD_BIT(i);
}
diff --git a/src/panfrost/lib/pan_shader.h b/src/panfrost/lib/pan_shader.h
index 616155ca368..4447bc7c3b3 100644
--- a/src/panfrost/lib/pan_shader.h
+++ b/src/panfrost/lib/pan_shader.h
@@ -50,20 +50,20 @@ pan_shader_prepare_midgard_rsd(const struct pan_shader_info *info,
{
assert((info->push.count & 3) == 0);
- rsd->properties.midgard.uniform_count = info->push.count / 4;
- rsd->properties.midgard.shader_has_side_effects = info->writes_global;
- rsd->properties.midgard.fp_mode = MALI_FP_MODE_GL_INF_NAN_ALLOWED;
+ rsd->properties.uniform_count = info->push.count / 4;
+ rsd->properties.shader_has_side_effects = info->writes_global;
+ rsd->properties.fp_mode = MALI_FP_MODE_GL_INF_NAN_ALLOWED;
/* For fragment shaders, work register count, early-z, reads at draw-time */
if (info->stage != MESA_SHADER_FRAGMENT) {
- rsd->properties.midgard.work_register_count = info->work_reg_count;
+ rsd->properties.work_register_count = info->work_reg_count;
} else {
- rsd->properties.midgard.shader_reads_tilebuffer =
+ rsd->properties.shader_reads_tilebuffer =
info->fs.outputs_read;
/* However, forcing early-z in the shader overrides draw-time */
- rsd->properties.midgard.force_early_z =
+ rsd->properties.force_early_z =
info->fs.early_fragment_tests;
}
}
@@ -84,8 +84,8 @@ pan_shader_prepare_midgard_rsd(const struct pan_shader_info *info,
* */
#define SET_PIXEL_KILL(kill, update) do { \
- rsd->properties.bifrost.pixel_kill_operation = MALI_PIXEL_KILL_## kill; \
- rsd->properties.bifrost.zs_update_operation = MALI_PIXEL_KILL_## update; \
+ rsd->properties.pixel_kill_operation = MALI_PIXEL_KILL_## kill; \
+ rsd->properties.zs_update_operation = MALI_PIXEL_KILL_## update; \
} while(0)
static inline void
@@ -98,7 +98,7 @@ pan_shader_classify_pixel_kill_coverage(const struct pan_shader_info *info,
bool depth = info->fs.writes_depth;
bool stencil = info->fs.writes_stencil;
- rsd->properties.bifrost.shader_modifies_coverage = coverage;
+ rsd->properties.shader_modifies_coverage = coverage;
if (force_early)
SET_PIXEL_KILL(FORCE_EARLY, STRONG_EARLY);
@@ -122,7 +122,7 @@ pan_shader_prepare_bifrost_rsd(const struct pan_shader_info *info,
rsd->preload.uniform_count = fau_count;
#if PAN_ARCH >= 7
- rsd->properties.bifrost.shader_register_allocation =
+ rsd->properties.shader_register_allocation =
(info->work_reg_count <= 32) ?
MALI_SHADER_REGISTER_ALLOCATION_32_PER_THREAD :
MALI_SHADER_REGISTER_ALLOCATION_64_PER_THREAD;
@@ -138,11 +138,11 @@ pan_shader_prepare_bifrost_rsd(const struct pan_shader_info *info,
pan_shader_classify_pixel_kill_coverage(info, rsd);
#if PAN_ARCH >= 7
- rsd->properties.bifrost.shader_wait_dependency_6 = info->bifrost.wait_6;
- rsd->properties.bifrost.shader_wait_dependency_7 = info->bifrost.wait_7;
+ rsd->properties.shader_wait_dependency_6 = info->bifrost.wait_6;
+ rsd->properties.shader_wait_dependency_7 = info->bifrost.wait_7;
#endif
- rsd->properties.bifrost.allow_forward_pixel_to_be_killed =
+ rsd->properties.allow_forward_pixel_to_be_killed =
!info->fs.sidefx;
rsd->preload.fragment.fragment_position = info->fs.reads_frag_coord;
@@ -159,8 +159,10 @@ pan_shader_prepare_bifrost_rsd(const struct pan_shader_info *info,
info->fs.reads_helper_invocation |
info->fs.sample_shading;
+#if PAN_ARCH >= 7
rsd->message_preload_1 = info->bifrost.messages[0];
rsd->message_preload_2 = info->bifrost.messages[1];
+#endif
break;
case MESA_SHADER_COMPUTE:
diff --git a/src/panfrost/lib/v4.xml b/src/panfrost/lib/v4.xml
new file mode 100644
index 00000000000..cc39b4f50b5
--- /dev/null
+++ b/src/panfrost/lib/v4.xml
@@ -0,0 +1,999 @@
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diff --git a/src/panfrost/lib/v5.xml b/src/panfrost/lib/v5.xml
new file mode 100644
index 00000000000..586fc7a0af5
--- /dev/null
+++ b/src/panfrost/lib/v5.xml
@@ -0,0 +1,1108 @@
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diff --git a/src/panfrost/lib/midgard.xml b/src/panfrost/lib/v6.xml
similarity index 68%
rename from src/panfrost/lib/midgard.xml
rename to src/panfrost/lib/v6.xml
index 8fc399bc4ea..8334b25b3b9 100644
--- a/src/panfrost/lib/midgard.xml
+++ b/src/panfrost/lib/v6.xml
@@ -1,5 +1,4 @@
-
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@@ -1414,6 +1084,9 @@
when in-place rendering is used with the AFBC block size differing
from the effective tile size (XXX: does v6 need a different workaround?) -->
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diff --git a/src/panfrost/lib/v7.xml b/src/panfrost/lib/v7.xml
new file mode 100644
index 00000000000..a7c144ba684
--- /dev/null
+++ b/src/panfrost/lib/v7.xml
@@ -0,0 +1,1333 @@
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diff --git a/src/panfrost/vulkan/panvk_vX_cmd_buffer.c b/src/panfrost/vulkan/panvk_vX_cmd_buffer.c
index e46a002d338..2e9bc35ed27 100644
--- a/src/panfrost/vulkan/panvk_vX_cmd_buffer.c
+++ b/src/panfrost/vulkan/panvk_vX_cmd_buffer.c
@@ -97,7 +97,7 @@ panvk_copy_fb_desc(struct panvk_cmd_buffer *cmdbuf, void *src)
{
const struct pan_fb_info *fbinfo = &cmdbuf->state.fb.info;
struct panvk_batch *batch = cmdbuf->state.batch;
- uint32_t size = pan_size(MULTI_TARGET_FRAMEBUFFER);
+ uint32_t size = pan_size(FRAMEBUFFER);
if (fbinfo->zs.view.zs || fbinfo->zs.view.s)
size += pan_size(ZS_CRC_EXTENSION);
@@ -118,7 +118,7 @@ panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf)
const struct pan_fb_info *fbinfo = &cmdbuf->state.fb.info;
#if PAN_ARCH <= 5
- uint32_t tmp_fbd[(pan_size(MULTI_TARGET_FRAMEBUFFER) +
+ uint32_t tmp_fbd[(pan_size(FRAMEBUFFER) +
pan_size(ZS_CRC_EXTENSION) +
(MAX_RTS * pan_size(RENDER_TARGET))) / 4];
#endif
@@ -209,7 +209,7 @@ panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf)
#if PAN_ARCH <= 5
panvk_copy_fb_desc(cmdbuf, tmp_fbd);
memcpy(batch->tiler.templ,
- pan_section_ptr(fbd, MULTI_TARGET_FRAMEBUFFER, TILER),
+ pan_section_ptr(fbd, FRAMEBUFFER, TILER),
pan_size(TILER_CONTEXT));
#endif
@@ -262,7 +262,7 @@ panvk_per_arch(cmd_alloc_fb_desc)(struct panvk_cmd_buffer *cmdbuf)
batch->fb.info = cmdbuf->state.framebuffer;
batch->fb.desc =
pan_pool_alloc_desc_aggregate(&cmdbuf->desc_pool.base,
- PAN_DESC(MULTI_TARGET_FRAMEBUFFER),
+ PAN_DESC(FRAMEBUFFER),
PAN_DESC_ARRAY(has_zs_ext ? 1 : 0, ZS_CRC_EXTENSION),
PAN_DESC_ARRAY(MAX2(fbinfo->rt_count, 1), RENDER_TARGET));
diff --git a/src/panfrost/vulkan/panvk_vX_cs.c b/src/panfrost/vulkan/panvk_vX_cs.c
index 0f25b66242f..13b5f84f855 100644
--- a/src/panfrost/vulkan/panvk_vX_cs.c
+++ b/src/panfrost/vulkan/panvk_vX_cs.c
@@ -388,9 +388,6 @@ panvk_per_arch(emit_vertex_job)(const struct panvk_pipeline *pipeline,
pan_section_pack(job, COMPUTE_JOB, DRAW, cfg) {
cfg.draw_descriptor_is_64b = true;
-#if PAN_ARCH == 5
- cfg.texture_descriptor_is_64b = true;
-#endif
cfg.state = pipeline->rsds[MESA_SHADER_VERTEX];
cfg.attributes = draw->stages[MESA_SHADER_VERTEX].attributes;
cfg.attribute_buffers = draw->attribute_bufs;
@@ -405,8 +402,6 @@ panvk_per_arch(emit_vertex_job)(const struct panvk_pipeline *pipeline,
cfg.textures = draw->textures;
cfg.samplers = draw->samplers;
}
-
- pan_section_pack(job, COMPUTE_JOB, DRAW_PADDING, cfg);
}
static void
@@ -450,9 +445,6 @@ panvk_emit_tiler_dcd(const struct panvk_pipeline *pipeline,
pan_pack(dcd, DRAW, cfg) {
cfg.four_components_per_vertex = true;
cfg.draw_descriptor_is_64b = true;
-#if PAN_ARCH == 5
- cfg.texture_descriptor_is_64b = true;
-#endif
cfg.front_face_ccw = pipeline->rast.front_ccw;
cfg.cull_front_face = pipeline->rast.cull_front_face;
cfg.cull_back_face = pipeline->rast.cull_back_face;
@@ -519,7 +511,6 @@ panvk_per_arch(emit_tiler_job)(const struct panvk_pipeline *pipeline,
pan_section_pack(job, TILER_JOB, TILER, cfg) {
cfg.address = draw->tiler_ctx->bifrost;
}
- pan_section_pack(job, TILER_JOB, DRAW_PADDING, padding);
pan_section_pack(job, TILER_JOB, PADDING, padding);
#endif
}
@@ -562,24 +553,24 @@ panvk_per_arch(emit_viewport)(const VkViewport *viewport,
}
#if PAN_ARCH >= 6
-static enum mali_bifrost_register_file_format
+static enum mali_register_file_format
bifrost_blend_type_from_nir(nir_alu_type nir_type)
{
switch(nir_type) {
case 0: /* Render target not in use */
return 0;
case nir_type_float16:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_F16;
+ return MALI_REGISTER_FILE_FORMAT_F16;
case nir_type_float32:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_F32;
+ return MALI_REGISTER_FILE_FORMAT_F32;
case nir_type_int32:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_I32;
+ return MALI_REGISTER_FILE_FORMAT_I32;
case nir_type_uint32:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
+ return MALI_REGISTER_FILE_FORMAT_U32;
case nir_type_int16:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_I16;
+ return MALI_REGISTER_FILE_FORMAT_I16;
case nir_type_uint16:
- return MALI_BIFROST_REGISTER_FILE_FORMAT_U16;
+ return MALI_REGISTER_FILE_FORMAT_U16;
default:
unreachable("Unsupported blend shader type for NIR alu type");
}
@@ -599,7 +590,7 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
if (!blend->rt_count || !rts->equation.color_mask) {
cfg.enable = false;
#if PAN_ARCH >= 6
- cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OFF;
+ cfg.internal.mode = MALI_BLEND_MODE_OFF;
#endif
continue;
}
@@ -609,10 +600,10 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
cfg.round_to_fb_precision = !dithered;
#if PAN_ARCH <= 5
- cfg.midgard.blend_shader = false;
+ cfg.blend_shader = false;
pan_blend_to_fixed_function_equation(blend->rts[rt].equation,
- &cfg.midgard.equation);
- cfg.midgard.constant =
+ &cfg.equation);
+ cfg.constant =
pan_blend_get_constant(pan_blend_constant_mask(blend->rts[rt].equation),
blend->constants);
#else
@@ -624,7 +615,7 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
chan_size = MAX2(format_desc->channel[i].size, chan_size);
pan_blend_to_fixed_function_equation(blend->rts[rt].equation,
- &cfg.bifrost.equation);
+ &cfg.equation);
/* Fixed point constant */
float fconst =
@@ -632,22 +623,22 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
blend->constants);
u16 constant = fconst * ((1 << chan_size) - 1);
constant <<= 16 - chan_size;
- cfg.bifrost.constant = constant;
+ cfg.constant = constant;
if (pan_blend_is_opaque(blend->rts[rt].equation))
- cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OPAQUE;
+ cfg.internal.mode = MALI_BLEND_MODE_OPAQUE;
else
- cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_FIXED_FUNCTION;
+ cfg.internal.mode = MALI_BLEND_MODE_FIXED_FUNCTION;
/* If we want the conversion to work properly,
* num_comps must be set to 4
*/
- cfg.bifrost.internal.fixed_function.num_comps = 4;
- cfg.bifrost.internal.fixed_function.conversion.memory_format =
+ cfg.internal.fixed_function.num_comps = 4;
+ cfg.internal.fixed_function.conversion.memory_format =
panfrost_format_to_bifrost_blend(pdev, rts->format, dithered);
- cfg.bifrost.internal.fixed_function.conversion.register_format =
+ cfg.internal.fixed_function.conversion.register_format =
bifrost_blend_type_from_nir(pipeline->fs.info.bifrost.blend[rt].type);
- cfg.bifrost.internal.fixed_function.rt = rt;
+ cfg.internal.fixed_function.rt = rt;
#endif
}
}
@@ -663,9 +654,9 @@ panvk_per_arch(emit_blend_constant)(const struct panvk_device *dev,
pan_pack(bd, BLEND, cfg) {
cfg.enable = false;
#if PAN_ARCH == 5
- cfg.midgard.constant = constant;
+ cfg.constant = constant;
#else
- cfg.bifrost.constant = constant * pipeline->blend.constant[rt].bifrost_factor;
+ cfg.constant = constant * pipeline->blend.constant[rt].bifrost_factor;
#endif
}
}
@@ -716,8 +707,8 @@ panvk_per_arch(emit_base_fs_rsd)(const struct panvk_device *dev,
(pipeline->zs.z_test && pipeline->zs.z_compare_func != MALI_FUNC_ALWAYS) ||
pipeline->zs.s_test;
- cfg.properties.midgard.work_register_count = info->work_reg_count;
- cfg.properties.midgard.force_early_z =
+ cfg.properties.work_register_count = info->work_reg_count;
+ cfg.properties.force_early_z =
info->fs.can_early_z && !pipeline->ms.alpha_to_coverage &&
pipeline->zs.z_compare_func == MALI_FUNC_ALWAYS;
@@ -726,15 +717,15 @@ panvk_per_arch(emit_base_fs_rsd)(const struct panvk_device *dev,
* when discarding even when the depth buffer is read-only, by
* lying to the hardware about the discard and setting the
* reads tilebuffer? flag to compensate */
- cfg.properties.midgard.shader_reads_tilebuffer =
+ cfg.properties.shader_reads_tilebuffer =
info->fs.outputs_read ||
(!zs_enabled && info->fs.can_discard);
- cfg.properties.midgard.shader_contains_discard =
+ cfg.properties.shader_contains_discard =
zs_enabled && info->fs.can_discard;
#else
uint8_t rt_written = pipeline->fs.info.outputs_written >> FRAG_RESULT_DATA0;
uint8_t rt_mask = pipeline->fs.rt_mask;
- cfg.properties.bifrost.allow_forward_pixel_to_kill =
+ cfg.properties.allow_forward_pixel_to_kill =
pipeline->fs.info.fs.can_fpk &&
!(rt_mask & ~rt_written) &&
!pipeline->ms.alpha_to_coverage &&
@@ -743,14 +734,14 @@ panvk_per_arch(emit_base_fs_rsd)(const struct panvk_device *dev,
} else {
#if PAN_ARCH == 5
cfg.shader.shader = 0x1;
- cfg.properties.midgard.work_register_count = 1;
+ cfg.properties.work_register_count = 1;
cfg.properties.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;
- cfg.properties.midgard.force_early_z = true;
+ cfg.properties.force_early_z = true;
#else
- cfg.properties.bifrost.shader_modifies_coverage = true;
- cfg.properties.bifrost.allow_forward_pixel_to_kill = true;
- cfg.properties.bifrost.allow_forward_pixel_to_be_killed = true;
- cfg.properties.bifrost.zs_update_operation = MALI_PIXEL_KILL_STRONG_EARLY;
+ cfg.properties.shader_modifies_coverage = true;
+ cfg.properties.allow_forward_pixel_to_kill = true;
+ cfg.properties.allow_forward_pixel_to_be_killed = true;
+ cfg.properties.zs_update_operation = MALI_PIXEL_KILL_STRONG_EARLY;
#endif
}
diff --git a/src/panfrost/vulkan/panvk_vX_descriptor_set.c b/src/panfrost/vulkan/panvk_vX_descriptor_set.c
index 4a68e7264cd..38a18f1d0dd 100644
--- a/src/panfrost/vulkan/panvk_vX_descriptor_set.c
+++ b/src/panfrost/vulkan/panvk_vX_descriptor_set.c
@@ -201,8 +201,8 @@ panvk_per_arch(set_texture_desc)(struct panvk_descriptor_set *set,
{
VK_FROM_HANDLE(panvk_image_view, view, pImageInfo->imageView);
-#if PAN_ARCH > 5
- memcpy(&((struct mali_bifrost_texture_packed *)set->textures)[idx],
+#if PAN_ARCH >= 6
+ memcpy(&((struct mali_texture_packed *)set->textures)[idx],
view->descs.tex, pan_size(TEXTURE));
#else
((mali_ptr *)set->textures)[idx] = view->bo->ptr.gpu;
@@ -218,7 +218,7 @@ panvk_per_arch(write_descriptor_set)(struct panvk_device *dev,
unsigned dest_offset = pDescriptorWrite->dstArrayElement;
unsigned binding = pDescriptorWrite->dstBinding;
struct mali_uniform_buffer_packed *ubos = set->ubos;
- struct mali_midgard_sampler_packed *samplers = set->samplers;
+ struct mali_sampler_packed *samplers = set->samplers;
unsigned src_offset = 0;
while (src_offset < pDescriptorWrite->descriptorCount &&
diff --git a/src/panfrost/vulkan/panvk_vX_device.c b/src/panfrost/vulkan/panvk_vX_device.c
index b607f6ce718..d04da043029 100644
--- a/src/panfrost/vulkan/panvk_vX_device.c
+++ b/src/panfrost/vulkan/panvk_vX_device.c
@@ -58,10 +58,10 @@ panvk_queue_submit_batch(struct panvk_queue *queue,
}
#else
if (batch->fb.desc.cpu) {
- void *tiler = pan_section_ptr(batch->fb.desc.cpu, MULTI_TARGET_FRAMEBUFFER, TILER);
+ void *tiler = pan_section_ptr(batch->fb.desc.cpu, FRAMEBUFFER, TILER);
memcpy(tiler, batch->tiler.templ, pan_size(TILER_CONTEXT));
/* All weights set to 0, nothing to do here */
- pan_section_pack(batch->fb.desc.cpu, MULTI_TARGET_FRAMEBUFFER, TILER_WEIGHTS, w);
+ pan_section_pack(batch->fb.desc.cpu, FRAMEBUFFER, TILER_WEIGHTS, w);
}
#endif
}
diff --git a/src/panfrost/vulkan/panvk_vX_meta_clear.c b/src/panfrost/vulkan/panvk_vX_meta_clear.c
index 337dac59c65..b62c78db3c7 100644
--- a/src/panfrost/vulkan/panvk_vX_meta_clear.c
+++ b/src/panfrost/vulkan/panvk_vX_meta_clear.c
@@ -115,16 +115,16 @@ panvk_meta_clear_attachments_emit_rsd(struct panfrost_device *pdev,
cfg.stencil_back = cfg.stencil_front;
#if PAN_ARCH >= 6
- cfg.properties.bifrost.allow_forward_pixel_to_be_killed = true;
- cfg.properties.bifrost.allow_forward_pixel_to_kill = true;
- cfg.properties.bifrost.zs_update_operation =
+ cfg.properties.allow_forward_pixel_to_be_killed = true;
+ cfg.properties.allow_forward_pixel_to_kill = true;
+ cfg.properties.zs_update_operation =
MALI_PIXEL_KILL_STRONG_EARLY;
- cfg.properties.bifrost.pixel_kill_operation =
+ cfg.properties.pixel_kill_operation =
MALI_PIXEL_KILL_FORCE_EARLY;
#else
- cfg.properties.midgard.shader_reads_tilebuffer = false;
- cfg.properties.midgard.work_register_count = shader_info->work_reg_count;
- cfg.properties.midgard.force_early_z = true;
+ cfg.properties.shader_reads_tilebuffer = false;
+ cfg.properties.work_register_count = shader_info->work_reg_count;
+ cfg.properties.force_early_z = true;
cfg.stencil_mask_misc.alpha_test_compare_function = MALI_FUNC_ALWAYS;
#endif
}
@@ -132,28 +132,22 @@ panvk_meta_clear_attachments_emit_rsd(struct panfrost_device *pdev,
pan_pack(rsd_ptr.cpu + pan_size(RENDERER_STATE), BLEND, cfg) {
cfg.round_to_fb_precision = true;
cfg.load_destination = false;
+ cfg.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
+ cfg.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
+ cfg.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
+ cfg.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
+ cfg.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
+ cfg.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
#if PAN_ARCH >= 6
- cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_OPAQUE;
- cfg.bifrost.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.bifrost.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.bifrost.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.bifrost.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.bifrost.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.bifrost.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.bifrost.equation.color_mask = 0xf;
- cfg.bifrost.internal.fixed_function.num_comps = 4;
- cfg.bifrost.internal.fixed_function.conversion.memory_format =
+ cfg.internal.mode = MALI_BLEND_MODE_OPAQUE;
+ cfg.equation.color_mask = 0xf;
+ cfg.internal.fixed_function.num_comps = 4;
+ cfg.internal.fixed_function.conversion.memory_format =
panfrost_format_to_bifrost_blend(pdev, format, false);
- cfg.bifrost.internal.fixed_function.conversion.register_format =
+ cfg.internal.fixed_function.conversion.register_format =
shader_info->bifrost.blend[rt].format;
#else
- cfg.midgard.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.midgard.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.midgard.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.midgard.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.midgard.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.midgard.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.midgard.equation.color_mask =
+ cfg.equation.color_mask =
(1 << util_format_get_nr_components(format)) - 1;
#endif
}
@@ -214,7 +208,6 @@ panvk_meta_clear_attachment_emit_dcd(struct pan_pool *pool,
cfg.push_uniforms = push_constants;
cfg.position = coords;
cfg.viewport = vpd;
- cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
}
}
diff --git a/src/panfrost/vulkan/panvk_vX_meta_copy.c b/src/panfrost/vulkan/panvk_vX_meta_copy.c
index 8597924e02f..6a6f13e39f3 100644
--- a/src/panfrost/vulkan/panvk_vX_meta_copy.c
+++ b/src/panfrost/vulkan/panvk_vX_meta_copy.c
@@ -141,7 +141,6 @@ panvk_meta_copy_emit_dcd(struct pan_pool *pool,
&cfg.varyings);
}
cfg.viewport = vpd;
- cfg.texture_descriptor_is_64b = PAN_ARCH <= 5;
cfg.textures = texture;
cfg.samplers = sampler;
}
@@ -218,8 +217,6 @@ panvk_meta_copy_emit_compute_job(struct pan_pool *desc_pool,
0, tsd, rsd, ubo, push_constants,
pan_section_ptr(job.cpu, COMPUTE_JOB, DRAW));
- pan_section_pack(job.cpu, COMPUTE_JOB, DRAW_PADDING, cfg);
-
panfrost_add_job(desc_pool, scoreboard, MALI_JOB_TYPE_COMPUTE,
false, false, 0, 0, &job, false);
return job;
@@ -278,17 +275,17 @@ panvk_meta_copy_to_img_emit_rsd(struct panfrost_device *pdev,
cfg.stencil_back = cfg.stencil_front;
#if PAN_ARCH >= 6
- cfg.properties.bifrost.allow_forward_pixel_to_be_killed = true;
- cfg.properties.bifrost.allow_forward_pixel_to_kill =
+ cfg.properties.allow_forward_pixel_to_be_killed = true;
+ cfg.properties.allow_forward_pixel_to_kill =
!partialwrite && !readstb;
- cfg.properties.bifrost.zs_update_operation =
+ cfg.properties.zs_update_operation =
MALI_PIXEL_KILL_STRONG_EARLY;
- cfg.properties.bifrost.pixel_kill_operation =
+ cfg.properties.pixel_kill_operation =
MALI_PIXEL_KILL_FORCE_EARLY;
#else
- cfg.properties.midgard.shader_reads_tilebuffer = readstb;
- cfg.properties.midgard.work_register_count = shader_info->work_reg_count;
- cfg.properties.midgard.force_early_z = true;
+ cfg.properties.shader_reads_tilebuffer = readstb;
+ cfg.properties.work_register_count = shader_info->work_reg_count;
+ cfg.properties.force_early_z = true;
cfg.stencil_mask_misc.alpha_test_compare_function = MALI_FUNC_ALWAYS;
#endif
}
@@ -296,42 +293,36 @@ panvk_meta_copy_to_img_emit_rsd(struct panfrost_device *pdev,
pan_pack(rsd_ptr.cpu + pan_size(RENDERER_STATE), BLEND, cfg) {
cfg.round_to_fb_precision = true;
cfg.load_destination = partialwrite;
+ cfg.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
+ cfg.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
+ cfg.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
+ cfg.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
+ cfg.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
+ cfg.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
#if PAN_ARCH >= 6
- cfg.bifrost.internal.mode =
+ cfg.internal.mode =
partialwrite ?
- MALI_BIFROST_BLEND_MODE_FIXED_FUNCTION :
- MALI_BIFROST_BLEND_MODE_OPAQUE;
- cfg.bifrost.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.bifrost.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.bifrost.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.bifrost.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.bifrost.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.bifrost.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.bifrost.equation.color_mask = partialwrite ? wrmask : 0xf;
- cfg.bifrost.internal.fixed_function.num_comps = 4;
+ MALI_BLEND_MODE_FIXED_FUNCTION :
+ MALI_BLEND_MODE_OPAQUE;
+ cfg.equation.color_mask = partialwrite ? wrmask : 0xf;
+ cfg.internal.fixed_function.num_comps = 4;
if (!raw) {
- cfg.bifrost.internal.fixed_function.conversion.memory_format =
+ cfg.internal.fixed_function.conversion.memory_format =
panfrost_format_to_bifrost_blend(pdev, fmt, false);
- cfg.bifrost.internal.fixed_function.conversion.register_format =
- MALI_BIFROST_REGISTER_FILE_FORMAT_F32;
+ cfg.internal.fixed_function.conversion.register_format =
+ MALI_REGISTER_FILE_FORMAT_F32;
} else {
unsigned imgtexelsz = util_format_get_blocksize(fmt);
- cfg.bifrost.internal.fixed_function.conversion.memory_format =
+ cfg.internal.fixed_function.conversion.memory_format =
panvk_meta_copy_img_bifrost_raw_format(imgtexelsz);
- cfg.bifrost.internal.fixed_function.conversion.register_format =
+ cfg.internal.fixed_function.conversion.register_format =
(imgtexelsz & 2) ?
- MALI_BIFROST_REGISTER_FILE_FORMAT_U16 :
- MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
+ MALI_REGISTER_FILE_FORMAT_U16 :
+ MALI_REGISTER_FILE_FORMAT_U32;
}
#else
- cfg.midgard.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.midgard.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.midgard.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.midgard.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC;
- cfg.midgard.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
- cfg.midgard.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
- cfg.midgard.equation.color_mask = wrmask;
+ cfg.equation.color_mask = wrmask;
#endif
}
@@ -540,11 +531,11 @@ panvk_meta_copy_img2img_shader(struct panfrost_device *pdev,
};
#if PAN_ARCH >= 6
- pan_pack(&inputs.bifrost.rt_conv[0], BIFROST_INTERNAL_CONVERSION, cfg) {
+ pan_pack(&inputs.bifrost.rt_conv[0], INTERNAL_CONVERSION, cfg) {
cfg.memory_format = (dstcompsz == 2 ? MALI_RG16UI : MALI_RG32UI) << 12;
cfg.register_format = dstcompsz == 2 ?
- MALI_BIFROST_REGISTER_FILE_FORMAT_U16 :
- MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
+ MALI_REGISTER_FILE_FORMAT_U16 :
+ MALI_REGISTER_FILE_FORMAT_U32;
}
inputs.bifrost.static_rt_conv = true;
#endif
@@ -1093,11 +1084,11 @@ panvk_meta_copy_buf2img_shader(struct panfrost_device *pdev,
};
#if PAN_ARCH >= 6
- pan_pack(&inputs.bifrost.rt_conv[0], BIFROST_INTERNAL_CONVERSION, cfg) {
+ pan_pack(&inputs.bifrost.rt_conv[0], INTERNAL_CONVERSION, cfg) {
cfg.memory_format = (imgcompsz == 2 ? MALI_RG16UI : MALI_RG32UI) << 12;
cfg.register_format = imgcompsz == 2 ?
- MALI_BIFROST_REGISTER_FILE_FORMAT_U16 :
- MALI_BIFROST_REGISTER_FILE_FORMAT_U32;
+ MALI_REGISTER_FILE_FORMAT_U16 :
+ MALI_REGISTER_FILE_FORMAT_U32;
}
inputs.bifrost.static_rt_conv = true;
#endif