From b73638ae5ed251cebda5f033517293aa01051d44 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 24 Aug 2022 11:29:46 -0700 Subject: [PATCH] iris: Allocate fixed amount of space for blend state. According to the simulator a cacheline of the blend state cache corresponds to 3 cachelines of L3 that are always filled regardless of the number of render targets in use. Allocate enough space to avoid pagefaults under simulation, since a scratch page isn't bound by default. Reviewed-by: Ian Romanick Part-of: --- src/gallium/drivers/iris/iris_state.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 4d66781e990..4cc840a1cb3 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6865,7 +6865,6 @@ iris_upload_dirty_render_state(struct iris_context *ice, struct iris_blend_state *cso_blend = ice->state.cso_blend; struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer; struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa; - const int header_dwords = GENX(BLEND_STATE_length); bool color_blend_zero = false; bool alpha_blend_zero = false; @@ -6881,7 +6880,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, uint32_t *blend_map = stream_state(batch, ice->state.dynamic_uploader, &ice->state.last_res.blend, - 4 * (header_dwords + rt_dwords), 64, &blend_offset); + 96, 64, &blend_offset); /* Copy of blend entries for merging dynamic changes. */ uint32_t blend_entries[4 * rt_dwords];