From b69b9b8eb2dc864c1728e97e0b576c5e83a57174 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 7 Mar 2025 21:26:08 +0000 Subject: [PATCH] amd/drm-shim: add gfx1201 Signed-off-by: Rhys Perry Reviewed-by: Georg Lehmann Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/drm-shim/amdgpu_devices.c | 131 +++++++++++++++++++++++++- src/amd/drm-shim/amdgpu_dump_states.c | 1 + 2 files changed, 131 insertions(+), 1 deletion(-) diff --git a/src/amd/drm-shim/amdgpu_devices.c b/src/amd/drm-shim/amdgpu_devices.c index 349bd0f6af6..c54461605b1 100644 --- a/src/amd/drm-shim/amdgpu_devices.c +++ b/src/amd/drm-shim/amdgpu_devices.c @@ -2054,7 +2054,136 @@ const struct amdgpu_device amdgpu_devices[] = { .max_allocation = UINT64_C(12355639296), }, }, - } + }, + { + .name = "gfx1201", + .radeon_family = CHIP_GFX1201, + .hw_ip_gfx = { + .hw_ip_version_major = 12, + .hw_ip_version_minor = 0, + .capabilities_flags = UINT64_C(0), + .ib_start_alignment = 32, + .ib_size_alignment = 32, + .available_rings = 0x1, + .ip_discovery_version = 0xc0001, + }, + .hw_ip_compute = { + .hw_ip_version_major = 12, + .hw_ip_version_minor = 0, + .capabilities_flags = UINT64_C(0), + .ib_start_alignment = 32, + .ib_size_alignment = 32, + .available_rings = 0xf, + .ip_discovery_version = 0xc0001, + }, + .fw_gfx_me = { + .ver = 2590, + .feature = 29, + }, + .fw_gfx_pfp = { + .ver = 2630, + .feature = 29, + }, + .fw_gfx_mec = { + .ver = 2800, + .feature = 29, + }, + .mmr_regs = { + 0x263e, 0xffffffff, 0x08200545, + }, + .mmr_reg_count = 1, + .dev = { + .device_id = 0x7550, + .chip_rev = 0x01, + .external_rev = 0x51, + .pci_rev = 0xc0, + .family = AMDGPU_FAMILY_GC_12_0_0, + .num_shader_engines = 4, + .num_shader_arrays_per_engine = 2, + .gpu_counter_freq = 100000, + .max_engine_clock = UINT64_C(2460000), + .max_memory_clock = UINT64_C(1258000), + .cu_active_number = 64, + .cu_ao_mask = 0x0, + .cu_bitmap = { + { 0xff, 0xff, 0x0, 0x0, }, + { 0xff, 0xff, 0x0, 0x0, }, + { 0xff, 0xff, 0x0, 0x0, }, + { 0xff, 0xff, 0x0, 0x0, }, + }, + .enabled_rb_pipes_mask = 0xffff, + .num_rb_pipes = 16, + .num_hw_gfx_contexts = 8, + .pcie_gen = 4, + .ids_flags = UINT64_C(0x0), + .virtual_address_offset = UINT64_C(0x10000), + .virtual_address_max = UINT64_C(0x800000000000), + .virtual_address_alignment = 4096, + .pte_fragment_size = 2097152, + .gart_page_size = 4096, + .ce_ram_size = 0, + .vram_type = 9, + .vram_bit_width = 256, + .vce_harvest_config = 0, + .gc_double_offchip_lds_buf = 64, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), + .prim_buf_size = 0, + .pos_buf_size = 0, + .cntl_sb_buf_size = 0, + .param_buf_size = 0, + .wave_front_size = 32, + .num_shader_visible_vgprs = 1536, + .num_cu_per_sh = 8, + .num_tcc_blocks = 32, + .gs_vgt_table_depth = 32, + .gs_prim_buffer_depth = 1792, + .max_gs_waves_per_vgt = 32, + .pcie_num_lanes = 8, + .cu_ao_bitmap = { + { 0x0, 0x0, 0x0, 0x0, }, + { 0x0, 0x0, 0x0, 0x0, }, + { 0x0, 0x0, 0x0, 0x0, }, + { 0x0, 0x0, 0x0, 0x0, }, + }, + .high_va_offset = UINT64_C(0xffff800000000000), + .high_va_max = UINT64_C(0xffffffffffbfe000), + .pa_sc_tile_steering_override = 0, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(500000), + .min_memory_clock = UINT64_C(96000), + .tcp_cache_size = 32, + .num_sqc_per_wgp = 1, + .sqc_data_cache_size = 16, + .sqc_inst_cache_size = 32, + .gl1c_cache_size = 256, + .gl2c_cache_size = 8192, + .mall_size = UINT64_C(67108864), + .enabled_rb_pipes_mask_hi = 0, + }, + .mem = { + .vram = { + .total_heap_size = UINT64_C(17095983104), + .usable_heap_size = UINT64_C(16543346688), + .heap_usage = UINT64_C(555782144), + .max_allocation = UINT64_C(12407510016), + }, + .cpu_accessible_vram = { + .total_heap_size = UINT64_C(268435456), + .usable_heap_size = UINT64_C(265252864), + .heap_usage = UINT64_C(4526080), + .max_allocation = UINT64_C(198939648), + }, + .gtt = { + .total_heap_size = UINT64_C(16785289216), + .usable_heap_size = UINT64_C(16769716224), + .heap_usage = UINT64_C(15622144), + .max_allocation = UINT64_C(12577287168), + }, + }, + }, }; const size_t num_amdgpu_devices = ARRAY_SIZE(amdgpu_devices); diff --git a/src/amd/drm-shim/amdgpu_dump_states.c b/src/amd/drm-shim/amdgpu_dump_states.c index e6e30f24453..196020125b1 100644 --- a/src/amd/drm-shim/amdgpu_dump_states.c +++ b/src/amd/drm-shim/amdgpu_dump_states.c @@ -151,6 +151,7 @@ amdgpu_dump_dev_info(int fd) FAMILY(GC_10_3_6), FAMILY(GC_10_3_7), FAMILY(GC_11_5_0), + FAMILY(GC_12_0_0), /* clang-format on */ #undef FAMILY };