From b5f53fdf3204257a824bc9ae6f4c62880674c23e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 20 Jun 2024 17:07:35 +0200 Subject: [PATCH] ac/nir/tess: Add tcs_inputs_read to LS output lowering. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit just adds the field, it will be taken into use in a following commit. Signed-off-by: Timur Kristóf Reviewed-by: Alyssa Rosenzweig Reviewed-by: Marek Olšák Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_nir.h | 1 + src/amd/common/ac_nir_lower_tess_io_to_mem.c | 8 ++++++++ src/amd/vulkan/nir/radv_nir_lower_io.c | 2 +- src/gallium/drivers/radeonsi/si_shader.c | 2 +- 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h index f146676b171..d896bebb2c7 100644 --- a/src/amd/common/ac_nir.h +++ b/src/amd/common/ac_nir.h @@ -77,6 +77,7 @@ void ac_nir_lower_ls_outputs_to_mem(nir_shader *ls, ac_nir_map_io_driver_location map, bool tcs_in_out_eq, + uint64_t tcs_inputs_read, uint64_t tcs_temp_only_inputs); void diff --git a/src/amd/common/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/ac_nir_lower_tess_io_to_mem.c index 813400fab81..1adfd8ba097 100644 --- a/src/amd/common/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_tess_io_to_mem.c @@ -124,6 +124,11 @@ typedef struct { */ uint64_t tcs_temp_only_inputs; + /* Bit mask of inputs read by the TCS, + * this is used for linking VS outputs to TCS inputs. + */ + uint64_t tcs_inputs_read; + /* Bit mask of TCS outputs read by TES. */ uint64_t tes_inputs_read; uint32_t tes_patch_inputs_read; @@ -969,12 +974,14 @@ void ac_nir_lower_ls_outputs_to_mem(nir_shader *shader, ac_nir_map_io_driver_location map, bool tcs_in_out_eq, + uint64_t tcs_inputs_read, uint64_t tcs_temp_only_inputs) { assert(shader->info.stage == MESA_SHADER_VERTEX); lower_tess_io_state state = { .tcs_in_out_eq = tcs_in_out_eq, + .tcs_inputs_read = tcs_inputs_read, .tcs_temp_only_inputs = tcs_in_out_eq ? tcs_temp_only_inputs : 0, .map_io = map, }; @@ -992,6 +999,7 @@ ac_nir_lower_hs_inputs_to_mem(nir_shader *shader, assert(shader->info.stage == MESA_SHADER_TESS_CTRL); lower_tess_io_state state = { + .tcs_inputs_read = shader->info.inputs_read, .tcs_in_out_eq = tcs_in_out_eq, .map_io = map, }; diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c index ab50beeccf0..46fc1a37c0e 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_io.c +++ b/src/amd/vulkan/nir/radv_nir_lower_io.c @@ -134,7 +134,7 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s if (nir->info.stage == MESA_SHADER_VERTEX) { if (info->vs.as_ls) { NIR_PASS_V(nir, ac_nir_lower_ls_outputs_to_mem, map_output, info->vs.tcs_in_out_eq, - info->vs.tcs_temp_only_input_mask); + info->vs.hs_inputs_read, info->vs.tcs_temp_only_input_mask); return true; } else if (info->vs.as_es) { NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, map_output, pdev->info.gfx_level, info->esgs_itemsize); diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index d5a2eca5d4b..647735f1f41 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -1841,7 +1841,7 @@ static bool si_lower_io_to_mem(struct si_shader *shader, nir_shader *nir, if (nir->info.stage == MESA_SHADER_VERTEX) { if (key->ge.as_ls) { NIR_PASS_V(nir, ac_nir_lower_ls_outputs_to_mem, si_map_io_driver_location, - key->ge.opt.same_patch_vertices, tcs_vgpr_only_inputs); + key->ge.opt.same_patch_vertices, ~0ULL, tcs_vgpr_only_inputs); return true; } else if (key->ge.as_es) { NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, si_map_io_driver_location,