From b577f8b547faa0024f689618477188e6ecd0777e Mon Sep 17 00:00:00 2001 From: Konstantin Seurer Date: Fri, 9 Jun 2023 10:16:39 +0200 Subject: [PATCH] radv/rt: Do not guard the raygen shader The condition will always evaluate to true because it's set this way by the prolog. Quake II RTX: Totals from 7 (10.00% of 70) affected shaders: Instrs: 30070 -> 30056 (-0.05%); split: -0.07%, +0.03% CodeSize: 163476 -> 163420 (-0.03%); split: -0.06%, +0.03% Latency: 80335 -> 83887 (+4.42%) InvThroughput: 16870 -> 17603 (+4.34%) Copies: 3191 -> 3215 (+0.75%) Branches: 1273 -> 1266 (-0.55%) PreSGPRs: 356 -> 354 (-0.56%) Reviewed-by: Friedrich Vock Part-of: --- src/amd/vulkan/radv_pipeline_rt.c | 4 ++-- src/amd/vulkan/radv_rt_shader.c | 22 ++++++++++++++-------- src/amd/vulkan/radv_shader.h | 2 +- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index dc6b6c47466..402131878d9 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -336,8 +336,8 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache, for (uint32_t i = 0; i < num_shaders; i++) { struct radv_pipeline_stage temp_stage = *stage; temp_stage.nir = shaders[i]; - radv_nir_lower_rt_abi(temp_stage.nir, pCreateInfo, &temp_stage.args, pipeline_key, - stack_size); + radv_nir_lower_rt_abi(temp_stage.nir, pCreateInfo, &temp_stage.args, pipeline_key, stack_size, + i > 0); radv_optimize_nir(temp_stage.nir, pipeline_key->optimisations_disabled); radv_postprocess_nir(device, pipeline_layout, pipeline_key, MESA_SHADER_NONE, &temp_stage); diff --git a/src/amd/vulkan/radv_rt_shader.c b/src/amd/vulkan/radv_rt_shader.c index 4eb4a2d21b1..ca83657aaa4 100644 --- a/src/amd/vulkan/radv_rt_shader.c +++ b/src/amd/vulkan/radv_rt_shader.c @@ -1631,7 +1631,7 @@ select_next_shader(nir_builder *b, nir_ssa_def *shader_va, unsigned wave_size) void radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateInfoKHR *pCreateInfo, const struct radv_shader_args *args, const struct radv_pipeline_key *key, - uint32_t *stack_size) + uint32_t *stack_size, bool resume_shader) { nir_builder b; nir_function_impl *impl = nir_shader_get_entrypoint(shader); @@ -1687,14 +1687,20 @@ radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateInfoKH nir_store_var(&b, vars.hit_kind, ac_nir_load_arg(&b, &args->ac, args->ac.rt.hit_kind), 1); /* guard the shader, so that only the correct invocations execute it */ - nir_ssa_def *shader_pc = ac_nir_load_arg(&b, &args->ac, args->ac.rt.shader_pc); - shader_pc = nir_pack_64_2x32(&b, shader_pc); - shader_pc = nir_ior_imm(&b, shader_pc, radv_get_rt_priority(shader->info.stage)); - nir_ssa_def *cond = nir_ieq(&b, shader_pc, shader_va); - nir_if *shader_guard = nir_push_if(&b, cond); - shader_guard->control = nir_selection_control_divergent_always_taken; + nir_if *shader_guard = NULL; + if (shader->info.stage != MESA_SHADER_RAYGEN || resume_shader) { + nir_ssa_def *shader_pc = ac_nir_load_arg(&b, &args->ac, args->ac.rt.shader_pc); + shader_pc = nir_pack_64_2x32(&b, shader_pc); + shader_pc = nir_ior_imm(&b, shader_pc, radv_get_rt_priority(shader->info.stage)); + + shader_guard = nir_push_if(&b, nir_ieq(&b, shader_pc, shader_va)); + shader_guard->control = nir_selection_control_divergent_always_taken; + } + nir_cf_reinsert(&list, b.cursor); - nir_pop_if(&b, shader_guard); + + if (shader_guard) + nir_pop_if(&b, shader_guard); /* select next shader */ b.cursor = nir_after_cf_list(&impl->body); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 7483c8b3d6e..9c7ebc4cde9 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -584,7 +584,7 @@ nir_shader *radv_parse_rt_stage(struct radv_device *device, void radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateInfoKHR *pCreateInfo, const struct radv_shader_args *args, const struct radv_pipeline_key *key, - uint32_t *stack_size); + uint32_t *stack_size, bool resume_shader); struct radv_pipeline_stage;