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intel/vec4: Drop all of the 64-bit varying code

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Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand
2019-07-20 08:17:59 -05:00
parent d03ec807a4
commit b539157504
4 changed files with 43 additions and 196 deletions
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src/intel/compiler/brw_vec4_nir.cpp
+7 -37
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@@ -407,6 +407,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
switch (instr->intrinsic) {
case nir_intrinsic_load_input: {
assert(nir_dest_bit_size(instr->dest) == 32);
/* We set EmitNoIndirectInput for VS */
unsigned load_offset = nir_src_as_uint(instr->src[0]);
@@ -417,53 +418,22 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
glsl_type::uvec4_type);
src = retype(src, dest.type);
bool is_64bit = nir_dest_bit_size(instr->dest) == 64;
if (is_64bit) {
dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
src.swizzle = BRW_SWIZZLE_XYZW;
shuffle_64bit_data(tmp, src, false);
emit(MOV(dest, src_reg(tmp)));
} else {
/* Swizzle source based on component layout qualifier */
src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
emit(MOV(dest, src));
}
/* Swizzle source based on component layout qualifier */
src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
emit(MOV(dest, src));
break;
}
case nir_intrinsic_store_output: {
assert(nir_src_bit_size(instr->src[0]) == 32);
unsigned store_offset = nir_src_as_uint(instr->src[1]);
int varying = instr->const_index[0] + store_offset;
bool is_64bit = nir_src_bit_size(instr->src[0]) == 64;
if (is_64bit) {
src_reg data;
src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_DF,
instr->num_components);
data = src_reg(this, glsl_type::dvec4_type);
shuffle_64bit_data(dst_reg(data), src, true);
src = retype(data, BRW_REGISTER_TYPE_F);
} else {
src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F,
instr->num_components);
}
src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F,
instr->num_components);
unsigned c = nir_intrinsic_component(instr);
output_reg[varying][c] = dst_reg(src);
output_num_components[varying][c] = instr->num_components;
unsigned num_components = instr->num_components;
if (is_64bit)
num_components *= 2;
output_reg[varying][c] = dst_reg(src);
output_num_components[varying][c] = MIN2(4, num_components);
if (is_64bit && num_components > 4) {
assert(num_components <= 8);
output_reg[varying + 1][c] = byte_offset(dst_reg(src), REG_SIZE);
output_num_components[varying + 1][c] = num_components - 4;
}
break;
}