diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h
index 69ff90472ae..16db749baea 100644
--- a/src/amd/common/ac_nir.h
+++ b/src/amd/common/ac_nir.h
@@ -91,13 +91,7 @@ bool
 ac_nir_lower_indirect_derefs(nir_shader *shader,
                              enum chip_class chip_class);
 
-typedef struct
-{
-   uint64_t nggc_inputs_read_by_pos;
-   uint64_t nggc_inputs_read_by_others;
-} ac_nir_ngg_config;
-
-ac_nir_ngg_config
+void
 ac_nir_lower_ngg_nogs(nir_shader *shader,
                       unsigned max_num_es_vertices,
                       unsigned num_vertices_per_primitive,
diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c
index 994aa42ecab..2aba6a076c6 100644
--- a/src/amd/common/ac_nir_lower_ngg.c
+++ b/src/amd/common/ac_nir_lower_ngg.c
@@ -1254,7 +1254,7 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c
       unreachable("Should be VS or TES.");
 }
 
-ac_nir_ngg_config
+void
 ac_nir_lower_ngg_nogs(nir_shader *shader,
                       unsigned max_num_es_vertices,
                       unsigned num_vertices_per_primitives,
@@ -1411,13 +1411,6 @@ ac_nir_lower_ngg_nogs(nir_shader *shader,
    } while (progress);
 
    shader->info.shared_size = state.total_lds_bytes;
-
-   ac_nir_ngg_config ret = {
-      .nggc_inputs_read_by_pos = state.inputs_needed_by_pos,
-      .nggc_inputs_read_by_others = state.inputs_needed_by_others,
-   };
-
-   return ret;
 }
 
 static nir_ssa_def *
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 5cc6c302aaf..4b806b12d2b 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -953,7 +953,6 @@ void radv_lower_ngg(struct radv_device *device, struct nir_shader *nir,
           nir->info.stage == MESA_SHADER_TESS_EVAL ||
           nir->info.stage == MESA_SHADER_GEOMETRY);
 
-   ac_nir_ngg_config out_conf = {0};
    const struct gfx10_ngg_info *ngg_info = &info->ngg_info;
    unsigned num_vertices_per_prim = 3;
 
@@ -1000,20 +999,19 @@ void radv_lower_ngg(struct radv_device *device, struct nir_shader *nir,
          export_prim_id = info->tes.outinfo.export_prim_id;
       }
 
-      out_conf =
-         ac_nir_lower_ngg_nogs(
-            nir,
-            max_vtx_in,
-            num_vertices_per_prim,
-            info->workgroup_size,
-            info->wave_size,
-            info->has_ngg_culling,
-            info->has_ngg_early_prim_export,
-            info->is_ngg_passthrough,
-            export_prim_id,
-            pl_key->vs.provoking_vtx_last,
-            false,
-            pl_key->vs.instance_rate_inputs);
+      ac_nir_lower_ngg_nogs(
+         nir,
+         max_vtx_in,
+         num_vertices_per_prim,
+         info->workgroup_size,
+         info->wave_size,
+         info->has_ngg_culling,
+         info->has_ngg_early_prim_export,
+         info->is_ngg_passthrough,
+         export_prim_id,
+         pl_key->vs.provoking_vtx_last,
+         false,
+         pl_key->vs.instance_rate_inputs);
    } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
       assert(info->is_ngg);
       ac_nir_lower_ngg_gs(