diff --git a/src/imagination/include/hwdef/pvr_hw_utils.h b/src/imagination/include/hwdef/pvr_hw_utils.h
new file mode 100644
index 00000000000..ff9f131ccb7
--- /dev/null
+++ b/src/imagination/include/hwdef/pvr_hw_utils.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2022 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef PVR_HW_UTILS_H
+#define PVR_HW_UTILS_H
+
+#include <stdint.h>
+#include <assert.h>
+
+#include "util/macros.h"
+
+#include "pvr_device_info.h"
+
+static inline uint32_t
+pvr_get_slc_cache_line_size(const struct pvr_device_info *dev_info)
+{
+   return PVR_GET_FEATURE_VALUE(dev_info, slc_cache_line_size_bits, 8U) / 8U;
+}
+
+static inline uint32_t pvr_get_max_user_vertex_output_components(
+   const struct pvr_device_info *dev_info)
+{
+   /* Default value based on the minimum value found in all existing cores. */
+   const uint32_t uvs_pba_entries =
+      PVR_GET_FEATURE_VALUE(dev_info, uvs_pba_entries, 160U);
+
+   /* Default value based on the minimum value found in all existing cores. */
+   const uint32_t uvs_banks = PVR_GET_FEATURE_VALUE(dev_info, uvs_banks, 2U);
+
+   if (uvs_banks <= 8U && uvs_pba_entries == 160U) {
+      ASSERTED const uint32_t tpu_parallel_instances =
+         PVR_GET_FEATURE_VALUE(dev_info, tpu_parallel_instances, 1U);
+
+      /* Cores with > 2 ppc support vertex sizes of >= 128 dwords */
+      assert(tpu_parallel_instances <= 2 ||
+             (dev_info->ident.b <= 36 || dev_info->ident.b == 46));
+
+      return 64U;
+   }
+
+   return 128U;
+}
+
+#endif /* PVR_HW_UTILS_H */
diff --git a/src/imagination/include/hwdef/rogue_hw_utils.h b/src/imagination/include/hwdef/rogue_hw_utils.h
index 4ed2136fe02..ca230185e3b 100644
--- a/src/imagination/include/hwdef/rogue_hw_utils.h
+++ b/src/imagination/include/hwdef/rogue_hw_utils.h
@@ -51,6 +51,8 @@
 #include "util/compiler.h"
 #include "util/macros.h"
 
+#include "pvr_hw_utils.h"
+
 static inline void
 rogue_get_isp_samples_per_tile_xy(const struct pvr_device_info *dev_info,
                                   uint32_t samples,
@@ -258,36 +260,6 @@ rogue_get_render_size_max(const struct pvr_device_info *dev_info)
 #define rogue_get_render_size_max_y(dev_info) \
    rogue_get_render_size_max(dev_info)
 
-static inline uint32_t
-pvr_get_slc_cache_line_size(const struct pvr_device_info *dev_info)
-{
-   return PVR_GET_FEATURE_VALUE(dev_info, slc_cache_line_size_bits, 8U) / 8U;
-}
-
-static inline uint32_t pvr_get_max_user_vertex_output_components(
-   const struct pvr_device_info *dev_info)
-{
-   /* Default value based on the minimum value found in all existing cores. */
-   const uint32_t uvs_pba_entries =
-      PVR_GET_FEATURE_VALUE(dev_info, uvs_pba_entries, 160U);
-
-   /* Default value based on the minimum value found in all existing cores. */
-   const uint32_t uvs_banks = PVR_GET_FEATURE_VALUE(dev_info, uvs_banks, 2U);
-
-   if (uvs_banks <= 8U && uvs_pba_entries == 160U) {
-      ASSERTED const uint32_t tpu_parallel_instances =
-         PVR_GET_FEATURE_VALUE(dev_info, tpu_parallel_instances, 1U);
-
-      /* Cores with > 2 ppc support vertex sizes of >= 128 dwords */
-      assert(tpu_parallel_instances <= 2 ||
-             (dev_info->ident.b <= 36 || dev_info->ident.b == 46));
-
-      return 64U;
-   }
-
-   return 128U;
-}
-
 static inline uint32_t
 rogue_max_compute_shared_registers(const struct pvr_device_info *dev_info)
 {
diff --git a/src/imagination/vulkan/pvr_device.c b/src/imagination/vulkan/pvr_device.c
index dce7b5c6730..0712a791f34 100644
--- a/src/imagination/vulkan/pvr_device.c
+++ b/src/imagination/vulkan/pvr_device.c
@@ -40,7 +40,7 @@
 #include <string.h>
 #include <vulkan/vulkan.h>
 
-#include "hwdef/rogue_hw_utils.h"
+#include "hwdef/pvr_hw_utils.h"
 #include "pco_uscgen_programs.h"
 #include "pvr_bo.h"
 #include "pvr_border.h"