From b23cc8c1d39c419b025870159083f444eca7c465 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 31 Oct 2024 08:09:02 +0100 Subject: [PATCH] radv: add missing L2 non-coherent image case for mipmaps with DCC/HTILE on GFX11 According to PAL, an image with DCC/HTILE and mipmaps isn't coherent with L2 when the mip level is in the metadata mip-tail region. This fix isn't super optimal because the driver should rely on the subresource range to determine if the mip level is in the mip-tail, but it's easier to backport. Upcoming commits will optimize that. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11939 Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_image.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index a7b66656870..24e6500d761 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -929,6 +929,18 @@ radv_image_is_l2_coherent(const struct radv_device *device, const struct radv_im if (pdev->info.gfx_level >= GFX12) { return true; /* Everything is coherent with TC L2. */ } else if (pdev->info.gfx_level >= GFX10) { + /* Add a special case for mips in the metadata mip-tail for GFX11. */ + if (pdev->info.gfx_level >= GFX11) { + if (image->vk.mip_levels > 1 && (radv_image_has_dcc(image) || radv_image_has_htile(image))) { + for (unsigned i = 0; i < image->plane_count; ++i) { + const struct radeon_surf *surf = &image->planes[i].surface; + + if (surf->num_meta_levels != image->vk.mip_levels) + return false; + } + } + } + return !pdev->info.tcc_rb_non_coherent && !radv_image_is_pipe_misaligned(device, image); } else if (pdev->info.gfx_level == GFX9) { if (image->vk.samples == 1 &&