From b1862a096468a2c29c96d7e9c1ea11b7265c3f0d Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 2 Mar 2018 16:02:58 -0800 Subject: [PATCH] intel/isl: Add initial data-structure support for miptails This commit just adds a miptail start field to isl_surf and wires it up in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code. We also add a minimum miptail LOD so that client drivers have a knob to control the miptails a bit. Reviewed-by: Topi Pohjolainen Reviewed-by: Paulo Zanoni Reviewed-by: Lionel Landwerlin Reviewed-by: Nanley Chery Part-of: --- src/intel/isl/isl.c | 5 +++++ src/intel/isl/isl.h | 11 +++++++++++ src/intel/isl/isl_emit_cpb.c | 5 +---- src/intel/isl/isl_emit_depth_stencil.c | 10 +++------- src/intel/isl/isl_surface_state.c | 5 +---- 5 files changed, 21 insertions(+), 15 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 5667854947b..18d81310ecd 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -2274,6 +2274,11 @@ isl_surf_init_s(const struct isl_device *dev, .array_pitch_el_rows = array_pitch_el_rows, .array_pitch_span = array_pitch_span, + /* We don't use miptails yet. The PRM recommends that you set "Mip Tail + * Start LOD" to 15 to prevent the hardware from trying to use them. + */ + .miptail_start_level = 15, + .usage = info->usage, }; diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index bffe96f828e..a9f17673135 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -1497,6 +1497,9 @@ struct isl_surf_init_info { /** Lower bound for isl_surf::alignment, in bytes. */ uint32_t min_alignment_B; + /** Lower bound for where to start the miptail */ + uint32_t min_miptail_start_level; + /** * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init() * will fail if this is misaligned or out of bounds. @@ -1597,6 +1600,14 @@ struct isl_surf { enum isl_array_pitch_span array_pitch_span; + /** + * Level at which the miptail starts. + * + * This value is inclusive in the sense that the miptail contains this + * level. + */ + uint32_t miptail_start_level; + /** Copy of isl_surf_init_info::usage. */ isl_surf_usage_flags_t usage; }; diff --git a/src/intel/isl/isl_emit_cpb.c b/src/intel/isl/isl_emit_cpb.c index 54d2c1fd9df..b85f4f57748 100644 --- a/src/intel/isl/isl_emit_cpb.c +++ b/src/intel/isl/isl_emit_cpb.c @@ -100,10 +100,7 @@ isl_genX(emit_cpb_control_s)(const struct isl_device *dev, void *batch, cpb.TiledMode = isl_encode_tiling[info->surf->tiling]; cpb.SurfaceBaseAddress = info->address; - /* We don't use miptails yet. The PRM recommends that you set "Mip Tail - * Start LOD" to 15 to prevent the hardware from trying to use them. - */ - cpb.MipTailStartLOD = 15; + cpb.MipTailStartLOD = info->surf->miptail_start_level; /* TODO: * * cpb.CPCBCompressionEnable is this CCS compression? Currently disabled diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index 943bc3578ba..840f1bc0856 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -170,7 +170,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #if GFX_VERx10 >= 125 db.TiledMode = isl_encode_tiling[info->depth_surf->tiling]; - db.MipTailStartLOD = 15; + db.MipTailStartLOD = info->depth_surf->miptail_start_level; db.CompressionMode = isl_aux_usage_has_ccs(info->hiz_usage); db.RenderCompressionFormat = isl_get_render_compression_format(info->depth_surf->format); @@ -178,11 +178,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, /* Gen9+ depth is always Y-tiled but it may be Y0, Yf, or Ys. */ assert(isl_tiling_is_any_y(info->depth_surf->tiling)); db.TiledResourceMode = isl_encode_tiling[info->depth_surf->tiling]; - - /* We don't use miptails yet. The PRM recommends that you set "Mip Tail - * Start LOD" to 15 to prevent the hardware from trying to use them. - */ - db.MipTailStartLOD = 15; + db.MipTailStartLOD = info->depth_surf->miptail_start_level; #elif GFX_VER >= 7 /* Gen7+ depth is always Y-tiled. We don't even have a bit for it */ #else @@ -244,7 +240,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #endif #if GFX_VER >= 12 sb.TiledMode = isl_encode_tiling[info->stencil_surf->tiling]; - sb.MipTailStartLOD = 15; + sb.MipTailStartLOD = info->stencil_surf->miptail_start_level; sb.StencilWriteEnable = true; sb.SurfaceType = SURFTYPE_2D; sb.Width = info->stencil_surf->logical_level0_px.width - 1; diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index c2cca13c82b..deac7fcf185 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -416,10 +416,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, } #if GFX_VER >= 9 - /* We don't use miptails yet. The PRM recommends that you set "Mip Tail - * Start LOD" to 15 to prevent the hardware from trying to use them. - */ - s.MipTailStartLOD = 15; + s.MipTailStartLOD = info->surf->miptail_start_level; #endif #if GFX_VERx10 >= 125