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aco/gfx10: optimize subgroupRotate(x, 32) and subgroupShuffleXor(x, 32)

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We don't have v_permlane64_b32 yet, but we can still optimize it using
shared vgprs. Using the DPP16 row mask, we can even avoid writing exec.

With v0 input/output and v24/v25 as shared vgprs, this results in:
v_mov_b32_dpp v24, v0 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0xf
v_mov_b32_dpp v25, v0 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
v_mov_b32_dpp v0, v24 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
v_mov_b32_dpp v0, v25 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0xf

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36390>
This commit is contained in:
Georg Lehmann
2025-07-26 13:54:17 +02:00
committed by Marge Bot
parent eb4df58a3d
commit b12db991eb
5 changed files with 46 additions and 2 deletions
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src/amd/compiler/aco_register_allocation.cpp
+4 -2
View File
@@ -575,7 +575,8 @@ get_subdword_operand_stride(amd_gfx_level gfx_level, const aco_ptr<Instruction>&
assert(gfx_level >= GFX8);
if (instr->isPseudo()) {
/* v_readfirstlane_b32 cannot use SDWA */
if (instr->opcode == aco_opcode::p_as_uniform)
if (instr->opcode == aco_opcode::p_as_uniform ||
instr->opcode == aco_opcode::p_permlane64_shared_vgpr)
return 4;
else
return rc.bytes() % 2 == 0 ? 2 : 1;
@@ -684,7 +685,8 @@ DefInfo::get_subdword_definition_info(Program* program, const aco_ptr<Instructio
stride = rc.bytes() % 2 == 0 ? 2 : 1;
if (instr->isPseudo()) {
if (instr->opcode == aco_opcode::p_interp_gfx11) {
if (instr->opcode == aco_opcode::p_interp_gfx11 ||
instr->opcode == aco_opcode::p_permlane64_shared_vgpr) {
rc = RegClass(RegType::vgpr, rc.size());
stride = 4;
}