diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 34534e9dd95..946c4250aa4 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -5483,6 +5483,17 @@ fixup_tg4(struct ir3_context *ctx)
    }
 }
 
+static bool
+is_empty(struct ir3 *ir)
+{
+   foreach_block (block, &ir->block_list) {
+      foreach_instr (instr, &block->instr_list) {
+         return instr->opc == OPC_END;
+      }
+   }
+   return true;
+}
+
 static void
 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
 {
@@ -6030,6 +6041,10 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
       so->constlen = MAX2(so->constlen, 8);
    }
 
+   if (so->type == MESA_SHADER_FRAGMENT) {
+      so->empty = is_empty(ir) && so->num_sampler_prefetch == 0;
+   }
+
    if (gl_shader_stage_is_compute(so->type)) {
       so->cs.local_invocation_id =
          ir3_find_sysval_regid(so, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index 8af15ff3986..12faf9310da 100644
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -853,6 +853,8 @@ struct ir3_shader_variant {
 
    bool post_depth_coverage;
 
+   bool empty;
+
    /* Are we using split or merged register file? */
    bool mergedregs;