From b06609e90324e8c445eb71eec39158a893c574c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Mon, 25 Jan 2021 18:37:29 +0100 Subject: [PATCH] aco: fix nir_intrinsic_ballot with wave32 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Found by inspection. Fixes: 21db083504fde3100f0b528f683a087357f5aaff ('aco/wave32: Allow setting the subgroup ballot size to 64-bit.') Reviewed-by: Timur Kristóf Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 0bf065acb8e..524f20662c0 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -8159,7 +8159,7 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) Temp src = get_ssa_temp(ctx, instr->src[0].ssa); Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); Definition tmp = bld.def(dst.regClass()); - Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass()); + Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(bld.lm); if (instr->src[0].ssa->bit_size == 1) { assert(src.regClass() == bld.lm); bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);