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radv: add radv_emit_shaders_prefetch()

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2017-10-16 17:48:42 +02:00
parent 0d85f4a9e2
commit af6985b309
1 changed files with 19 additions and 12 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+19 -12
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@@ -620,6 +620,23 @@ radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
}
static void
radv_emit_shaders_prefetch(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline)
{
radv_emit_shader_prefetch(cmd_buffer,
pipeline->shaders[MESA_SHADER_VERTEX]);
radv_emit_shader_prefetch(cmd_buffer,
pipeline->shaders[MESA_SHADER_TESS_CTRL]);
radv_emit_shader_prefetch(cmd_buffer,
pipeline->shaders[MESA_SHADER_TESS_EVAL]);
radv_emit_shader_prefetch(cmd_buffer,
pipeline->shaders[MESA_SHADER_GEOMETRY]);
radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
radv_emit_shader_prefetch(cmd_buffer,
pipeline->shaders[MESA_SHADER_FRAGMENT]);
}
static void
radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline,
@@ -629,8 +646,6 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
unsigned export_count;
radv_emit_shader_prefetch(cmd_buffer, shader);
export_count = MAX2(1, outinfo->param_exports);
radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
S_0286C4_VS_EXPORT_COUNT(export_count - 1));
@@ -676,8 +691,6 @@ radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
{
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
radv_emit_shader_prefetch(cmd_buffer, shader);
radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
outinfo->esgs_itemsize / 4);
radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
@@ -694,8 +707,6 @@ radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
uint32_t rsrc2 = shader->rsrc2;
radv_emit_shader_prefetch(cmd_buffer, shader);
radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
radeon_emit(cmd_buffer->cs, va >> 8);
radeon_emit(cmd_buffer->cs, va >> 40);
@@ -716,8 +727,6 @@ radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
{
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
radv_emit_shader_prefetch(cmd_buffer, shader);
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
radeon_emit(cmd_buffer->cs, va >> 8);
@@ -863,8 +872,6 @@ radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
radv_emit_shader_prefetch(cmd_buffer, gs);
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
radeon_emit(cmd_buffer->cs, va >> 8);
@@ -918,8 +925,6 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
radv_emit_shader_prefetch(cmd_buffer, ps);
radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
radeon_emit(cmd_buffer->cs, va >> 8);
radeon_emit(cmd_buffer->cs, va >> 40);
@@ -996,6 +1001,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
radv_emit_fragment_shader(cmd_buffer, pipeline);
radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
radv_emit_shaders_prefetch(cmd_buffer, pipeline);
cmd_buffer->scratch_size_needed =
MAX2(cmd_buffer->scratch_size_needed,
pipeline->max_waves * pipeline->scratch_bytes_per_wave);