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radv: use vk_optimize_depth_stencil_state() for optimal settings

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For apps that aren't optimized.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36168>
This commit is contained in:
Samuel Pitoiset
2025-07-16 17:03:48 +02:00
committed by Marge Bot
parent 79c02a3388
commit af22d5c97d
1 changed files with 30 additions and 34 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+30 -34
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@@ -10920,33 +10920,31 @@ radv_emit_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer)
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_rendering_state *render = &cmd_buffer->state.render;
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
struct vk_depth_stencil_state ds = d->vk.ds;
const bool stencil_test_enable =
d->vk.ds.stencil.test_enable && (render->ds_att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
vk_optimize_depth_stencil_state(&ds, render->ds_att_aspects, true);
const uint32_t db_depth_control =
S_028800_Z_ENABLE(d->vk.ds.depth.test_enable ? 1 : 0) |
S_028800_Z_WRITE_ENABLE(d->vk.ds.depth.write_enable ? 1 : 0) | S_028800_ZFUNC(d->vk.ds.depth.compare_op) |
S_028800_DEPTH_BOUNDS_ENABLE(d->vk.ds.depth.bounds_test.enable ? 1 : 0) |
S_028800_STENCIL_ENABLE(stencil_test_enable) | S_028800_BACKFACE_ENABLE(stencil_test_enable) |
S_028800_STENCILFUNC(d->vk.ds.stencil.front.op.compare) |
S_028800_STENCILFUNC_BF(d->vk.ds.stencil.back.op.compare);
S_028800_Z_ENABLE(ds.depth.test_enable ? 1 : 0) | S_028800_Z_WRITE_ENABLE(ds.depth.write_enable ? 1 : 0) |
S_028800_ZFUNC(ds.depth.compare_op) | S_028800_DEPTH_BOUNDS_ENABLE(ds.depth.bounds_test.enable ? 1 : 0) |
S_028800_STENCIL_ENABLE(ds.stencil.test_enable) | S_028800_BACKFACE_ENABLE(ds.stencil.test_enable) |
S_028800_STENCILFUNC(ds.stencil.front.op.compare) | S_028800_STENCILFUNC_BF(ds.stencil.back.op.compare);
const uint32_t db_stencil_control =
S_02842C_STENCILFAIL(radv_translate_stencil_op(d->vk.ds.stencil.front.op.fail)) |
S_02842C_STENCILZPASS(radv_translate_stencil_op(d->vk.ds.stencil.front.op.pass)) |
S_02842C_STENCILZFAIL(radv_translate_stencil_op(d->vk.ds.stencil.front.op.depth_fail)) |
S_02842C_STENCILFAIL_BF(radv_translate_stencil_op(d->vk.ds.stencil.back.op.fail)) |
S_02842C_STENCILZPASS_BF(radv_translate_stencil_op(d->vk.ds.stencil.back.op.pass)) |
S_02842C_STENCILZFAIL_BF(radv_translate_stencil_op(d->vk.ds.stencil.back.op.depth_fail));
S_02842C_STENCILFAIL(radv_translate_stencil_op(ds.stencil.front.op.fail)) |
S_02842C_STENCILZPASS(radv_translate_stencil_op(ds.stencil.front.op.pass)) |
S_02842C_STENCILZFAIL(radv_translate_stencil_op(ds.stencil.front.op.depth_fail)) |
S_02842C_STENCILFAIL_BF(radv_translate_stencil_op(ds.stencil.back.op.fail)) |
S_02842C_STENCILZPASS_BF(radv_translate_stencil_op(ds.stencil.back.op.pass)) |
S_02842C_STENCILZFAIL_BF(radv_translate_stencil_op(ds.stencil.back.op.depth_fail));
const uint32_t depth_bounds_min = fui(d->vk.ds.depth.bounds_test.min);
const uint32_t depth_bounds_max = fui(d->vk.ds.depth.bounds_test.max);
const uint32_t depth_bounds_min = fui(ds.depth.bounds_test.min);
const uint32_t depth_bounds_max = fui(ds.depth.bounds_test.max);
if (pdev->info.gfx_level >= GFX12) {
const bool force_s_valid =
stencil_test_enable && ((d->vk.ds.stencil.front.op.pass != d->vk.ds.stencil.front.op.depth_fail) ||
(d->vk.ds.stencil.back.op.pass != d->vk.ds.stencil.back.op.depth_fail));
ds.stencil.test_enable && ((ds.stencil.front.op.pass != ds.stencil.front.op.depth_fail) ||
(ds.stencil.back.op.pass != ds.stencil.back.op.depth_fail));
radeon_begin(cmd_buffer->cs);
gfx12_begin_context_regs();
@@ -10955,22 +10953,21 @@ radv_emit_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer)
gfx12_opt_set_context_reg(cmd_buffer, R_028070_DB_DEPTH_CONTROL, RADV_TRACKED_DB_DEPTH_CONTROL, db_depth_control);
if (stencil_test_enable) {
if (ds.stencil.test_enable) {
gfx12_opt_set_context_reg(cmd_buffer, R_028074_DB_STENCIL_CONTROL, RADV_TRACKED_DB_STENCIL_CONTROL,
db_stencil_control);
gfx12_opt_set_context_reg(
cmd_buffer, R_028088_DB_STENCIL_REF, RADV_TRACKED_DB_STENCIL_REF,
S_028088_TESTVAL(d->vk.ds.stencil.front.reference) | S_028088_TESTVAL_BF(d->vk.ds.stencil.back.reference));
S_028088_TESTVAL(ds.stencil.front.reference) | S_028088_TESTVAL_BF(ds.stencil.back.reference));
gfx12_opt_set_context_reg2(cmd_buffer, R_028090_DB_STENCIL_READ_MASK, RADV_TRACKED_DB_STENCIL_READ_MASK,
S_028090_TESTMASK(d->vk.ds.stencil.front.compare_mask) |
S_028090_TESTMASK_BF(d->vk.ds.stencil.back.compare_mask),
S_028094_WRITEMASK(d->vk.ds.stencil.front.write_mask) |
S_028094_WRITEMASK_BF(d->vk.ds.stencil.back.write_mask));
gfx12_opt_set_context_reg2(
cmd_buffer, R_028090_DB_STENCIL_READ_MASK, RADV_TRACKED_DB_STENCIL_READ_MASK,
S_028090_TESTMASK(ds.stencil.front.compare_mask) | S_028090_TESTMASK_BF(ds.stencil.back.compare_mask),
S_028094_WRITEMASK(ds.stencil.front.write_mask) | S_028094_WRITEMASK_BF(ds.stencil.back.write_mask));
}
if (d->vk.ds.depth.bounds_test.enable) {
if (ds.depth.bounds_test.enable) {
gfx12_opt_set_context_reg2(cmd_buffer, R_028050_DB_DEPTH_BOUNDS_MIN, RADV_TRACKED_DB_DEPTH_BOUNDS_MIN,
depth_bounds_min, depth_bounds_max);
}
@@ -10981,21 +10978,20 @@ radv_emit_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer)
radeon_opt_set_context_reg(cmd_buffer, R_028800_DB_DEPTH_CONTROL, RADV_TRACKED_DB_DEPTH_CONTROL,
db_depth_control);
if (stencil_test_enable) {
if (ds.stencil.test_enable) {
radeon_opt_set_context_reg(cmd_buffer, R_02842C_DB_STENCIL_CONTROL, RADV_TRACKED_DB_STENCIL_CONTROL,
db_stencil_control);
radeon_opt_set_context_reg2(
cmd_buffer, R_028430_DB_STENCILREFMASK, RADV_TRACKED_DB_STENCILREFMASK,
S_028430_STENCILTESTVAL(d->vk.ds.stencil.front.reference) |
S_028430_STENCILMASK(d->vk.ds.stencil.front.compare_mask) |
S_028430_STENCILWRITEMASK(d->vk.ds.stencil.front.write_mask) | S_028430_STENCILOPVAL(1),
S_028434_STENCILTESTVAL_BF(d->vk.ds.stencil.back.reference) |
S_028434_STENCILMASK_BF(d->vk.ds.stencil.back.compare_mask) |
S_028434_STENCILWRITEMASK_BF(d->vk.ds.stencil.back.write_mask) | S_028434_STENCILOPVAL_BF(1));
S_028430_STENCILTESTVAL(ds.stencil.front.reference) | S_028430_STENCILMASK(ds.stencil.front.compare_mask) |
S_028430_STENCILWRITEMASK(ds.stencil.front.write_mask) | S_028430_STENCILOPVAL(1),
S_028434_STENCILTESTVAL_BF(ds.stencil.back.reference) |
S_028434_STENCILMASK_BF(ds.stencil.back.compare_mask) |
S_028434_STENCILWRITEMASK_BF(ds.stencil.back.write_mask) | S_028434_STENCILOPVAL_BF(1));
}
if (d->vk.ds.depth.bounds_test.enable) {
if (ds.depth.bounds_test.enable) {
radeon_opt_set_context_reg2(cmd_buffer, R_028020_DB_DEPTH_BOUNDS_MIN, RADV_TRACKED_DB_DEPTH_BOUNDS_MIN,
depth_bounds_min, depth_bounds_max);
}