diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index b1f7f959e1d..55ecf449e8f 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1407,6 +1407,13 @@ iris_init_render_context(struct iris_batch *batch)
       p.DX10OGLBorderModeforYCRCB = true;
       p.DX10OGLBorderModeforYCRCBMask = true;
    }
+
+   if (intel_device_info_is_bmg_g31(devinfo)) {
+      iris_emit_reg(batch, GENX(CACHE_MODE_0), reg) {
+         reg.MsaaFastClearEnabled = true;
+         reg.MsaaFastClearEnabledMask = true;
+      }
+   }
 #endif
 
 #if GFX_VER >= 30
diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c
index 2d389d3e3be..439b13a269a 100644
--- a/src/intel/vulkan/genX_init_state.c
+++ b/src/intel/vulkan/genX_init_state.c
@@ -522,6 +522,15 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
 #endif
    }
 
+#if GFX_VER == 20
+   if (intel_device_info_is_bmg_g31(devinfo)) {
+      anv_batch_write_reg(batch, GENX(CACHE_MODE_0), cm0) {
+         cm0.MsaaFastClearEnabled = true;
+         cm0.MsaaFastClearEnabledMask = true;
+      }
+   }
+#endif
+
 #if INTEL_NEEDS_WA_1806527549
    /* Wa_1806527549 says to disable the following HiZ optimization when the
     * depth buffer is D16_UNORM. We've found the WA to help with more depth