diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index bbb72bc6043..c53591740ad 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -106,6 +106,17 @@ unsigned ac_pipe_config_to_num_pipes(unsigned pipe_config)
    }
 }
 
+unsigned ac_get_dcc_min_compressed_block_size(const struct radeon_info *info)
+{
+   /* This should typically match the request size of the memory type. DIMMs have 64B minimum
+    * request size, which means compressing 64B to 32B has no benefit, while GDDR and HBM have
+    * 32B minimum request size. Sometimes a different size is used depending on the data fabric,
+    * etc.
+    */
+   return info->has_dedicated_vram || info->family == CHIP_GFX1151 ?
+            V_028C78_MIN_BLOCK_SIZE_32B : V_028C78_MIN_BLOCK_SIZE_64B;
+}
+
 bool ac_modifier_has_dcc(uint64_t modifier)
 {
    return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 5f812d47b52..032449b95a5 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -445,6 +445,7 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf
                        const struct ac_surf_config *config, enum radeon_surf_mode mode,
                        struct radeon_surf *surf);
 void ac_surface_zero_dcc_fields(struct radeon_surf *surf);
+unsigned ac_get_dcc_min_compressed_block_size(const struct radeon_info *info);
 unsigned ac_pipe_config_to_num_pipes(unsigned pipe_config);
 
 void ac_surface_apply_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf,
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 89011b30a6c..0aa889202a7 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1475,29 +1475,12 @@ radv_get_dcc_max_uncompressed_block_size(const struct radv_device *device, const
    return V_028C78_MAX_BLOCK_SIZE_256B;
 }
 
-static unsigned
-get_dcc_min_compressed_block_size(const struct radv_device *device)
-{
-   const struct radv_physical_device *pdev = radv_device_physical(device);
-
-   if (!pdev->info.has_dedicated_vram) {
-      /* amdvlk: [min-compressed-block-size] should be set to 32 for
-       * dGPU and 64 for APU because all of our APUs to date use
-       * DIMMs which have a request granularity size of 64B while all
-       * other chips have a 32B request size.
-       */
-      return V_028C78_MIN_BLOCK_SIZE_64B;
-   }
-
-   return V_028C78_MIN_BLOCK_SIZE_32B;
-}
-
 static uint32_t
 radv_init_dcc_control_reg(struct radv_device *device, struct radv_image_view *iview)
 {
    const struct radv_physical_device *pdev = radv_device_physical(device);
    unsigned max_uncompressed_block_size = radv_get_dcc_max_uncompressed_block_size(device, iview->image);
-   unsigned min_compressed_block_size = get_dcc_min_compressed_block_size(device);
+   unsigned min_compressed_block_size = ac_get_dcc_min_compressed_block_size(&pdev->info);
    unsigned max_compressed_block_size;
    unsigned independent_128b_blocks;
    unsigned independent_64b_blocks;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 879042554cf..49c33e22eba 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2615,13 +2615,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa
    bool round_mode = ntype != V_028C70_NUMBER_UNORM && ntype != V_028C70_NUMBER_SNORM &&
                      ntype != V_028C70_NUMBER_SRGB &&
                      format != V_028C70_COLOR_8_24 && format != V_028C70_COLOR_24_8;
-   /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
-    * 64 for APU because all of our APUs to date use DIMMs which have
-    * a request granularity size of 64B while all other chips have a
-    * 32B request size */
-   unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
-   if (!sctx->screen->info.has_dedicated_vram)
-      min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
+   unsigned min_compressed_block_size = ac_get_dcc_min_compressed_block_size(&sctx->screen->info);
 
    surf->cb_color_info = S_028C70_COMP_SWAP(swap) |
                          S_028C70_BLEND_CLAMP(blend_clamp) |