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intel/compiler: Use a struct for brw_compile_tes parameters

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Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>
This commit is contained in:
Caio Oliveira
2021-03-23 15:03:50 -07:00
committed by Marge Bot
parent 7372a48a4a
commit acf2d3c78b
5 changed files with 69 additions and 43 deletions
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src/intel/compiler/brw_shader.cpp
+15 -19
View File
@@ -1328,16 +1328,15 @@ backend_shader::invalidate_analysis(brw::analysis_dependency_class c)
extern "C" const unsigned *
brw_compile_tes(const struct brw_compiler *compiler,
void *log_data,
void *mem_ctx,
const struct brw_tes_prog_key *key,
const struct brw_vue_map *input_vue_map,
struct brw_tes_prog_data *prog_data,
nir_shader *nir,
struct brw_compile_stats *stats,
char **error_str)
brw_compile_tes_params *params)
{
const struct intel_device_info *devinfo = compiler->devinfo;
nir_shader *nir = params->nir;
const struct brw_tes_prog_key *key = params->key;
const struct brw_vue_map *input_vue_map = params->input_vue_map;
struct brw_tes_prog_data *prog_data = params->prog_data;
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
const bool debug_enabled = INTEL_DEBUG(DEBUG_TES);
const unsigned *assembly;
@@ -1361,8 +1360,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
assert(output_size_bytes >= 1);
if (output_size_bytes > GFX7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
params->error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
return NULL;
}
@@ -1423,19 +1421,18 @@ brw_compile_tes(const struct brw_compiler *compiler,
}
if (is_scalar) {
fs_visitor v(compiler, log_data, mem_ctx, &key->base,
fs_visitor v(compiler, params->log_data, mem_ctx, &key->base,
&prog_data->base.base, nir, 8,
debug_enabled);
if (!v.run_tes()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
params->error_str = ralloc_strdup(mem_ctx, v.fail_msg);
return NULL;
}
prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_generator g(compiler, log_data, mem_ctx,
fs_generator g(compiler, params->log_data, mem_ctx,
&prog_data->base.base, false, MESA_SHADER_TESS_EVAL);
if (unlikely(debug_enabled)) {
g.enable_debug(ralloc_asprintf(mem_ctx,
@@ -1446,27 +1443,26 @@ brw_compile_tes(const struct brw_compiler *compiler,
}
g.generate_code(v.cfg, 8, v.shader_stats,
v.performance_analysis.require(), stats);
v.performance_analysis.require(), params->stats);
g.add_const_data(nir->constant_data, nir->constant_data_size);
assembly = g.get_assembly();
} else {
brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
brw::vec4_tes_visitor v(compiler, params->log_data, key, prog_data,
nir, mem_ctx, debug_enabled);
if (!v.run()) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
params->error_str = ralloc_strdup(mem_ctx, v.fail_msg);
return NULL;
}
if (unlikely(debug_enabled))
v.dump_instructions();
assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
assembly = brw_vec4_generate_assembly(compiler, params->log_data, mem_ctx, nir,
&prog_data->base, v.cfg,
v.performance_analysis.require(),
stats, debug_enabled);
params->stats, debug_enabled);
}
return assembly;