From ac867af0997b3552b2b1faf912df8647172a0e55 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Sat, 22 Jul 2023 15:43:54 +0800 Subject: [PATCH] radeonsi: share si_get_tcs_out_patch_stride with aco MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move it out of llvm to be shared with aco. Reviewed-by: Marek Olšák Signed-off-by: Qiang Yu Part-of: --- src/gallium/drivers/radeonsi/si_shader.c | 9 +++++++++ .../drivers/radeonsi/si_shader_internal.h | 1 + .../drivers/radeonsi/si_shader_llvm_tess.c | 20 ++----------------- 3 files changed, 12 insertions(+), 18 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index f93dad3acc1..18783f0cf4d 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -3524,3 +3524,12 @@ nir_shader *si_get_prev_stage_nir_shader(struct si_shader *shader, return nir; } + +unsigned si_get_tcs_out_patch_stride(const struct si_shader_info *info) +{ + unsigned tcs_out_vertices = info->base.tess.tcs_vertices_out; + unsigned vertex_stride = util_last_bit64(info->outputs_written) * 4; + unsigned num_patch_outputs = util_last_bit64(info->patch_outputs_written); + + return tcs_out_vertices * vertex_stride + num_patch_outputs * 4; +} diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h index d5e00987a8f..9d392d2e672 100644 --- a/src/gallium/drivers/radeonsi/si_shader_internal.h +++ b/src/gallium/drivers/radeonsi/si_shader_internal.h @@ -135,6 +135,7 @@ nir_shader *si_get_prev_stage_nir_shader(struct si_shader *shader, struct si_shader *prev_shader, struct si_shader_args *args, bool *free_nir); +unsigned si_get_tcs_out_patch_stride(const struct si_shader_info *info); /* gfx10_shader_ngg.c */ unsigned gfx10_ngg_get_vertices_per_prim(struct si_shader *shader); diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c index a215dc96f32..00a341f2a94 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c @@ -46,23 +46,6 @@ LLVMValueRef si_get_rel_patch_id(struct si_shader_context *ctx) * All three shaders VS(LS), TCS, TES share the same LDS space. */ -static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx) -{ - assert(ctx->stage == MESA_SHADER_TESS_CTRL); - - return util_last_bit64(ctx->shader->selector->info.outputs_written) * 4; -} - -static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx) -{ - const struct si_shader_info *info = &ctx->shader->selector->info; - unsigned tcs_out_vertices = info->base.tess.tcs_vertices_out; - unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx); - unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->info.patch_outputs_written); - unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride + num_patch_outputs * 4; - return LLVMConstInt(ctx->ac.i32, patch_dw_stride, 0); -} - static LLVMValueRef get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx) { return si_unpack_param(ctx, ctx->args->vs_state_bits, 10, 14); @@ -71,7 +54,8 @@ static LLVMValueRef get_tcs_out_patch0_patch_data_offset(struct si_shader_contex static LLVMValueRef get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx) { LLVMValueRef patch0_patch_data_offset = get_tcs_out_patch0_patch_data_offset(ctx); - LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx); + unsigned patch_dw_stride = si_get_tcs_out_patch_stride(&ctx->shader->selector->info); + LLVMValueRef patch_stride = LLVMConstInt(ctx->ac.i32, patch_dw_stride, 0); LLVMValueRef rel_patch_id = si_get_rel_patch_id(ctx); return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);