From ac262c351f0c6e304ae589936425ff05303e9f82 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 10 Oct 2025 10:12:38 +0200 Subject: [PATCH] amd,radv: add ac_emit_cond_exec() Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_cmdbuf.c | 20 ++++++++++++++++++++ src/amd/common/ac_cmdbuf.h | 4 ++++ src/amd/vulkan/radv_cmd_buffer.c | 16 +++++++++------- src/amd/vulkan/radv_cs.c | 24 ------------------------ src/amd/vulkan/radv_cs.h | 2 -- 5 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/amd/common/ac_cmdbuf.c b/src/amd/common/ac_cmdbuf.c index 44eb71befce..b852a7a5832 100644 --- a/src/amd/common/ac_cmdbuf.c +++ b/src/amd/common/ac_cmdbuf.c @@ -857,3 +857,23 @@ ac_init_graphics_preamble_state(const struct ac_preamble_state *state, gfx6_init_graphics_preamble_state(state, pm4); } } + +void +ac_emit_cond_exec(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level, + uint64_t va, uint32_t count) +{ + ac_cmdbuf_begin(cs); + if (gfx_level >= GFX7) { + ac_cmdbuf_emit(PKT3(PKT3_COND_EXEC, 3, 0)); + ac_cmdbuf_emit(va); + ac_cmdbuf_emit(va >> 32); + ac_cmdbuf_emit(0); + ac_cmdbuf_emit(count); + } else { + ac_cmdbuf_emit(PKT3(PKT3_COND_EXEC, 2, 0)); + ac_cmdbuf_emit(va); + ac_cmdbuf_emit(va >> 32); + ac_cmdbuf_emit(count); + } + ac_cmdbuf_end(); +} diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h index c001d6d7751..92ef38ffd57 100644 --- a/src/amd/common/ac_cmdbuf.h +++ b/src/amd/common/ac_cmdbuf.h @@ -97,6 +97,10 @@ void ac_init_graphics_preamble_state(const struct ac_preamble_state *state, struct ac_pm4_state *pm4); +void +ac_emit_cond_exec(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level, + uint64_t va, uint32_t count); + #ifdef __cplusplus } #endif diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 0f1b2775f15..079652a783b 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4639,7 +4639,7 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_ if (requires_cond_exec) { uint64_t va = radv_get_tc_compat_zrange_va(image, iview->vk.base_mip_level); - radv_emit_cond_exec(device, cmd_buffer->cs, va, 3 /* SET_CONTEXT_REG size */); + ac_emit_cond_exec(cmd_buffer->cs->b, pdev->info.gfx_level, va, 3 /* SET_CONTEXT_REG size */); } radeon_begin(cmd_buffer->cs); @@ -5592,6 +5592,7 @@ static void radv_gfx12_emit_hiz_wa_full(struct radv_cmd_buffer *cmd_buffer) { const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); + const struct radv_physical_device *pdev = radv_device_physical(device); const struct radv_rendering_state *render = &cmd_buffer->state.render; const struct radv_image_view *iview = render->ds_att.iview; const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; @@ -5626,7 +5627,7 @@ radv_gfx12_emit_hiz_wa_full(struct radv_cmd_buffer *cmd_buffer) } else { const uint64_t va = radv_get_hiz_valid_va(iview->image, iview->vk.base_mip_level); - radv_emit_cond_exec(device, cmd_buffer->cs, va, num_dwords); + ac_emit_cond_exec(cmd_buffer->cs->b, pdev->info.gfx_level, va, num_dwords); radv_gfx12_override_hiz_enable(cmd_buffer, true); } @@ -10099,7 +10100,7 @@ radv_cs_emit_compute_predication(const struct radv_device *device, struct radv_c radv_emit_copy_data_imm(pdev, cs, 1, inv_va); /* If the API predication VA == 0, skip next command. */ - radv_emit_cond_exec(device, cs, va, 6 /* 1x COPY_DATA size */); + ac_emit_cond_exec(cs->b, pdev->info.gfx_level, va, 6 /* 1x COPY_DATA size */); /* Write 0 to the new predication VA (when the API condition != 0) */ radv_emit_copy_data_imm(pdev, cs, 0, inv_va); @@ -10108,7 +10109,7 @@ radv_cs_emit_compute_predication(const struct radv_device *device, struct radv_c va = inv_va; } - radv_emit_cond_exec(device, cs, va, dwords); + ac_emit_cond_exec(cs->b, pdev->info.gfx_level, va, dwords); } ALWAYS_INLINE static void @@ -10799,8 +10800,8 @@ radv_emit_indirect_taskmesh_draw_packets(const struct radv_device *device, struc &cmd_state->mec_inv_pred_emitted, ace_predication_size); if (workaround_cond_va) { - radv_emit_cond_exec(device, ace_cs, info->count_va, - 6 + 11 * num_views /* 1x COPY_DATA + Nx DISPATCH_TASKMESH_INDIRECT_MULTI_ACE */); + ac_emit_cond_exec(ace_cs->b, pdev->info.gfx_level, info->count_va, + 6 + 11 * num_views /* 1x COPY_DATA + Nx DISPATCH_TASKMESH_INDIRECT_MULTI_ACE */); radeon_begin(ace_cs); radeon_emit(PKT3(PKT3_COPY_DATA, 4, 0)); @@ -10827,7 +10828,8 @@ radv_emit_indirect_taskmesh_draw_packets(const struct radv_device *device, struc } if (workaround_cond_va) { - radv_emit_cond_exec(device, ace_cs, workaround_cond_va, 6 * num_views /* Nx DISPATCH_TASKMESH_DIRECT_ACE */); + ac_emit_cond_exec(ace_cs->b, pdev->info.gfx_level, workaround_cond_va, + 6 * num_views /* Nx DISPATCH_TASKMESH_DIRECT_ACE */); for (unsigned v = 0; v < num_views; ++v) { radv_cs_emit_dispatch_taskmesh_direct_ace_packet(device, cmd_state, ace_cs, 0, 0, 0); diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c index ecec3bb7285..3e7caad9386 100644 --- a/src/amd/vulkan/radv_cs.c +++ b/src/amd/vulkan/radv_cs.c @@ -583,30 +583,6 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e radeon_end(); } -void -radv_emit_cond_exec(const struct radv_device *device, struct radv_cmd_stream *cs, uint64_t va, uint32_t count) -{ - const struct radv_physical_device *pdev = radv_device_physical(device); - const enum amd_gfx_level gfx_level = pdev->info.gfx_level; - - radeon_begin(cs); - - if (gfx_level >= GFX7) { - radeon_emit(PKT3(PKT3_COND_EXEC, 3, 0)); - radeon_emit(va); - radeon_emit(va >> 32); - radeon_emit(0); - radeon_emit(count); - } else { - radeon_emit(PKT3(PKT3_COND_EXEC, 2, 0)); - radeon_emit(va); - radeon_emit(va >> 32); - radeon_emit(count); - } - - radeon_end(); -} - void radv_cs_write_data_imm(struct radv_cmd_stream *cs, unsigned engine_sel, uint64_t va, uint32_t imm) { diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index b7aae402896..261141f9bd1 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -403,8 +403,6 @@ void radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream * uint32_t *flush_cnt, uint64_t flush_va, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va); -void radv_emit_cond_exec(const struct radv_device *device, struct radv_cmd_stream *cs, uint64_t va, uint32_t count); - void radv_cs_write_data_imm(struct radv_cmd_stream *cs, unsigned engine_sel, uint64_t va, uint32_t imm); static inline void