diff --git a/src/gallium/frontends/rusticl/core/kernel.rs b/src/gallium/frontends/rusticl/core/kernel.rs
index 09ab0bd4b29..21a604c7192 100644
--- a/src/gallium/frontends/rusticl/core/kernel.rs
+++ b/src/gallium/frontends/rusticl/core/kernel.rs
@@ -919,10 +919,20 @@ impl Kernel {
                     } else {
                         let format = mem.pipe_format;
                         let (formats, orders) = if arg.kind == KernelArgType::Image {
-                            iviews.push(res.pipe_image_view(format, false, app_img_info.as_ref()));
+                            iviews.push(res.pipe_image_view(
+                                format,
+                                false,
+                                mem.pipe_image_host_access(),
+                                app_img_info.as_ref(),
+                            ));
                             (&mut img_formats, &mut img_orders)
                         } else if arg.kind == KernelArgType::RWImage {
-                            iviews.push(res.pipe_image_view(format, true, app_img_info.as_ref()));
+                            iviews.push(res.pipe_image_view(
+                                format,
+                                true,
+                                mem.pipe_image_host_access(),
+                                app_img_info.as_ref(),
+                            ));
                             (&mut img_formats, &mut img_orders)
                         } else {
                             sviews.push((res.clone(), format, app_img_info));
diff --git a/src/gallium/frontends/rusticl/core/memory.rs b/src/gallium/frontends/rusticl/core/memory.rs
index c7f3c3b888f..55cf3747f4a 100644
--- a/src/gallium/frontends/rusticl/core/memory.rs
+++ b/src/gallium/frontends/rusticl/core/memory.rs
@@ -1231,6 +1231,19 @@ impl Mem {
 
         Ok(())
     }
+
+    pub fn pipe_image_host_access(&self) -> u16 {
+        // those flags are all mutually exclusive
+        (if bit_check(self.flags, CL_MEM_HOST_READ_ONLY) {
+            PIPE_IMAGE_ACCESS_READ
+        } else if bit_check(self.flags, CL_MEM_HOST_WRITE_ONLY) {
+            PIPE_IMAGE_ACCESS_WRITE
+        } else if bit_check(self.flags, CL_MEM_HOST_NO_ACCESS) {
+            0
+        } else {
+            PIPE_IMAGE_ACCESS_READ_WRITE
+        }) as u16
+    }
 }
 
 impl Drop for Mem {
diff --git a/src/gallium/frontends/rusticl/mesa/pipe/resource.rs b/src/gallium/frontends/rusticl/mesa/pipe/resource.rs
index 521b8c5f908..3b8075610ca 100644
--- a/src/gallium/frontends/rusticl/mesa/pipe/resource.rs
+++ b/src/gallium/frontends/rusticl/mesa/pipe/resource.rs
@@ -82,6 +82,7 @@ impl PipeResource {
         &self,
         format: pipe_format,
         read_write: bool,
+        host_access: u16,
         app_img_info: Option<&AppImgInfo>,
     ) -> pipe_image_view {
         let u = if let Some(app_img_info) = app_img_info {
@@ -130,7 +131,7 @@ impl PipeResource {
         pipe_image_view {
             resource: self.pipe(),
             format: format,
-            access: access,
+            access: access | host_access,
             shader_access: shader_access,
             u: u,
         }