diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 610c9db083f..eedef604d1e 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -9779,6 +9779,7 @@ radv_dgc_before_dispatch(struct radv_cmd_buffer *cmd_buffer) { struct radv_compute_pipeline *pipeline = cmd_buffer->state.compute_pipeline; struct radv_shader *compute_shader = cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]; + bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline; /* We will have run the DGC patch shaders before, so we can assume that there is something to * flush. Otherwise, we just split radv_dispatch in two. One pre-dispatch and another one @@ -9791,6 +9792,17 @@ radv_dgc_before_dispatch(struct radv_cmd_buffer *cmd_buffer) si_emit_cache_flush(cmd_buffer); radv_upload_compute_shader_descriptors(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE); + + if (pipeline_is_dirty) { + /* Raytracing uses compute shaders but has separate bind points and pipelines. + * So if we set compute userdata & shader registers we should dirty the raytracing + * ones and the other way around. + * + * We only need to do this when the pipeline is dirty because when we switch between + * the two we always need to switch pipelines. + */ + radv_mark_descriptor_sets_dirty(cmd_buffer, VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR); + } } static void @@ -9805,17 +9817,6 @@ radv_dgc_after_dispatch(struct radv_cmd_buffer *cmd_buffer) radv_emit_shader_prefetch(cmd_buffer, compute_shader); } - if (pipeline_is_dirty) { - /* Raytracing uses compute shaders but has separate bind points and pipelines. - * So if we set compute userdata & shader registers we should dirty the raytracing - * ones and the other way around. - * - * We only need to do this when the pipeline is dirty because when we switch between - * the two we always need to switch pipelines. - */ - radv_mark_descriptor_sets_dirty(cmd_buffer, VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR); - } - if (compute_shader->info.cs.regalloc_hang_bug) cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;