From ab21ce46a693c7b948ff76d4a342589ab3b9a644 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 5 May 2022 13:11:56 +0200 Subject: [PATCH] radv: update TF_RING_size to a per-SE size on GFX11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Part-of: --- src/amd/vulkan/radv_device.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 2537e06cc99..2a0a2a26e70 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -3825,6 +3825,11 @@ radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs, radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo); if (queue->device->physical_device->rad_info.gfx_level >= GFX7) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX11) { + /* TF_RING_SIZE is per SE on GFX11. */ + tf_ring_size /= queue->device->physical_device->rad_info.max_se; + } + radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE, S_030938_SIZE(tf_ring_size)); radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, tf_va >> 8);