From ab076e19ed93b1240f21dcfaf48e0dbe70322966 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 13 Jan 2021 19:57:35 -0800 Subject: [PATCH] intel/genxml: Define 3DSTATE_SUBSLICE_HASH_TABLE command for Gen12 and Gen12.5. This command allows programming custom pixel hashing tables controlling the balancing of load across pixel pipes. Rather confusingly 3DSTATE_SLICE_TABLE_STATE_POINTERS was serving the same purpose on Gen11: A pixel is mapped to the pixel pipe with index specified by the entry in the table corresponding to the LSBs of the pixel coordinates [Yes you read right the entries are neither subslice nor slice indices!]. Either a 2-way or a 3-way table can be programmed based on whether the platform has two or three pixel pipes per slice. In addition the 16x8 tables defined below can hold two separate 8x8 tables when in DUAL_TABLE mode (which AFAIA is only useful for platforms with multiple asymmetric slices -- I.e. no production platforms as of today to my knowledge). Reviewed-by: Jason Ekstrand Part-of: --- src/intel/genxml/gen12.xml | 30 ++++++++++++++++++++++++++++++ src/intel/genxml/gen125.xml | 30 ++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index 83af084854f..903d6e2a4b6 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -2566,6 +2566,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index 6ec73cd4b90..8c2b0600181 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -2574,6 +2574,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +