From a9fd4fa26c64275168946fa4d29ad066c0da7bc4 Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Wed, 23 Jun 2021 13:55:06 +0300 Subject: [PATCH] turnip: early exit in tu6_draw_common to save cpu cycles Improves Zink + drawoverhead perf up to 4% Before: 1, DrawElements ( 1 VBO| 0 UBO| 0 ) w/ no state change, 3981 1, DrawElements ( 1 VBO| 0 UBO| 0 ) w/ no state change, 3977 After: 1, DrawElements ( 1 VBO| 0 UBO| 0 ) w/ no state change, 4136 1, DrawElements ( 1 VBO| 0 UBO| 0 ) w/ no state change, 4163 Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/vulkan/tu_cmd_buffer.c | 31 ++++++++++++++++++---------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index 2de699ada27..cedca454f63 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -110,6 +110,8 @@ void tu_emit_cache_flush_renderpass(struct tu_cmd_buffer *cmd_buffer, struct tu_cs *cs) { + if (!cmd_buffer->state.renderpass_cache.flush_bits) + return; tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.renderpass_cache.flush_bits); cmd_buffer->state.renderpass_cache.flush_bits = 0; } @@ -3624,18 +3626,9 @@ tu6_draw_common(struct tu_cmd_buffer *cmd, { const struct tu_pipeline *pipeline = cmd->state.pipeline; VkResult result; - bool dirty_lrz = cmd->state.dirty & (TU_CMD_DIRTY_LRZ | TU_CMD_DIRTY_RB_DEPTH_CNTL | TU_CMD_DIRTY_RB_STENCIL_CNTL); - - struct tu_descriptor_state *descriptors_state = - &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS]; tu_emit_cache_flush_renderpass(cmd, cs); - if (dirty_lrz) { - cmd->state.lrz.state = tu6_build_lrz(cmd); - cmd->state.depth_plane_state = tu6_build_depth_plane_z_mode(cmd); - } - tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0( .primitive_restart = pipeline->ia.primitive_restart && indexed, @@ -3643,6 +3636,24 @@ tu6_draw_common(struct tu_cmd_buffer *cmd, .tess_upper_left_domain_origin = pipeline->tess.upper_left_domain_origin)); + bool has_tess = + pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT; + + /* Early exit if there is nothing to emit, saves CPU cycles */ + if (!(cmd->state.dirty & ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD) && + !has_tess) + return VK_SUCCESS; + + bool dirty_lrz = cmd->state.dirty & (TU_CMD_DIRTY_LRZ | TU_CMD_DIRTY_RB_DEPTH_CNTL | TU_CMD_DIRTY_RB_STENCIL_CNTL); + + struct tu_descriptor_state *descriptors_state = + &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS]; + + if (dirty_lrz) { + cmd->state.lrz.state = tu6_build_lrz(cmd); + cmd->state.depth_plane_state = tu6_build_depth_plane_z_mode(cmd); + } + if (cmd->state.dirty & TU_CMD_DIRTY_GRAS_SU_CNTL) { struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_GRAS_SU_CNTL, 2); tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = cmd->state.gras_su_cntl)); @@ -3674,8 +3685,6 @@ tu6_draw_common(struct tu_cmd_buffer *cmd, tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT); } - bool has_tess = - pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT; struct tu_draw_state tess_consts = {}; if (has_tess) { uint64_t tess_factor_iova = 0;