diff --git a/src/intel/compiler/brw_compile_gs.cpp b/src/intel/compiler/brw_compile_gs.cpp
index becafac6858..69055e58503 100644
--- a/src/intel/compiler/brw_compile_gs.cpp
+++ b/src/intel/compiler/brw_compile_gs.cpp
@@ -58,7 +58,8 @@ brw_compile_gs(const struct brw_compiler *compiler,
                        &c.input_vue_map, inputs_read,
                        nir->info.separate_shader, 1);
 
-   brw_nir_apply_key(nir, compiler, &key->base, 8);
+   brw_nir_apply_key(nir, compiler, &key->base,
+                     brw_geometry_stage_dispatch_width(compiler->devinfo));
    brw_nir_lower_vue_inputs(nir, &c.input_vue_map);
    brw_nir_lower_vue_outputs(nir);
    brw_postprocess_nir(nir, compiler, debug_enabled,
diff --git a/src/intel/compiler/brw_compile_tcs.cpp b/src/intel/compiler/brw_compile_tcs.cpp
index c0f294608c8..cfee80652a9 100644
--- a/src/intel/compiler/brw_compile_tcs.cpp
+++ b/src/intel/compiler/brw_compile_tcs.cpp
@@ -65,7 +65,8 @@ brw_compile_tcs(const struct brw_compiler *compiler,
                             nir->info.outputs_written,
                             nir->info.patch_outputs_written);
 
-   brw_nir_apply_key(nir, compiler, &key->base, 8);
+   brw_nir_apply_key(nir, compiler, &key->base,
+                     brw_geometry_stage_dispatch_width(compiler->devinfo));
    brw_nir_lower_vue_inputs(nir, &input_vue_map);
    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map,
                              key->_tes_primitive_mode);
diff --git a/src/intel/compiler/brw_compile_vs.cpp b/src/intel/compiler/brw_compile_vs.cpp
index 221a96b830d..5f103c65e4a 100644
--- a/src/intel/compiler/brw_compile_vs.cpp
+++ b/src/intel/compiler/brw_compile_vs.cpp
@@ -26,7 +26,8 @@ brw_compile_vs(const struct brw_compiler *compiler,
    prog_data->base.base.ray_queries = nir->info.ray_queries;
    prog_data->base.base.total_scratch = 0;
 
-   brw_nir_apply_key(nir, compiler, &key->base, 8);
+   brw_nir_apply_key(nir, compiler, &key->base,
+                     brw_geometry_stage_dispatch_width(compiler->devinfo));
 
    prog_data->inputs_read = nir->info.inputs_read;
    prog_data->double_inputs_read = nir->info.vs.double_inputs;
diff --git a/src/intel/compiler/brw_private.h b/src/intel/compiler/brw_private.h
index e054e420f0e..d573d06a656 100644
--- a/src/intel/compiler/brw_private.h
+++ b/src/intel/compiler/brw_private.h
@@ -78,6 +78,8 @@ inline bool brw_simd_any_compiled(const brw_simd_selection_state &state)
    return brw_simd_first_compiled(state) >= 0;
 }
 
+unsigned brw_geometry_stage_dispatch_width(const struct intel_device_info *devinfo);
+
 bool brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd);
 
 void brw_simd_mark_compiled(brw_simd_selection_state &state, unsigned simd, bool spilled);
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index dba0a9bccfa..763dce438da 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -624,7 +624,8 @@ brw_compile_tes(const struct brw_compiler *compiler,
    nir->info.inputs_read = key->inputs_read;
    nir->info.patch_inputs_read = key->patch_inputs_read;
 
-   brw_nir_apply_key(nir, compiler, &key->base, 8);
+   brw_nir_apply_key(nir, compiler, &key->base,
+                     brw_geometry_stage_dispatch_width(compiler->devinfo));
    brw_nir_lower_tes_inputs(nir, input_vue_map);
    brw_nir_lower_vue_outputs(nir);
    brw_postprocess_nir(nir, compiler, debug_enabled,
diff --git a/src/intel/compiler/brw_simd_selection.cpp b/src/intel/compiler/brw_simd_selection.cpp
index 05f9394c0d4..86ed1c28e84 100644
--- a/src/intel/compiler/brw_simd_selection.cpp
+++ b/src/intel/compiler/brw_simd_selection.cpp
@@ -41,6 +41,14 @@ brw_required_dispatch_width(const struct shader_info *info)
    }
 }
 
+unsigned
+brw_geometry_stage_dispatch_width(const struct intel_device_info *devinfo)
+{
+   if (devinfo->ver >= 20)
+      return 16;
+   return 8;
+}
+
 static inline bool
 test_bit(unsigned mask, unsigned bit) {
    return mask & (1u << bit);