From a86f32a1aea0c2dabb01421d8b93290cc5cef626 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 4 Jul 2025 13:06:38 -0400 Subject: [PATCH] etnaviv,r600,v3d,virgl: report correct nir_options::support_indirect_* These drivers set lower_all_io_to_temps = true, which means all indirect access is always lowered except TCS, which is skipped by nir_lower_io_vars_to_temporaries. Based on that, these drivers have never received indirect IO for non-TCS shaders. Reviewed-by: Alyssa Rosenzweig Part-of: --- src/gallium/drivers/etnaviv/etnaviv_compiler.c | 2 -- src/gallium/drivers/r600/r600_pipe_common.c | 4 ++-- src/gallium/drivers/v3d/v3d_screen.c | 11 ----------- src/gallium/drivers/virgl/virgl_screen.c | 2 +- 4 files changed, 3 insertions(+), 16 deletions(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c b/src/gallium/drivers/etnaviv/etnaviv_compiler.c index e02923e5c41..61daec95db4 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c @@ -84,8 +84,6 @@ etna_compiler_create(const char *renderer, const struct etna_core_info *info) .lower_ufind_msb = true, .has_uclz = true, .no_integers = info->halti < 2, - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), - .support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), }; compiler->regs = etna_ra_setup(compiler); diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c index b638249dc06..23dfc2ca7f5 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.c +++ b/src/gallium/drivers/r600/r600_pipe_common.c @@ -1220,8 +1220,8 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen, rscreen->nir_options_fs = rscreen->nir_options; rscreen->nir_options_fs.lower_all_io_to_temps = true; - rscreen->nir_options.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES); - rscreen->nir_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES); + rscreen->nir_options.support_indirect_inputs = BITFIELD_BIT(PIPE_SHADER_TESS_CTRL); + rscreen->nir_options.support_indirect_outputs = BITFIELD_BIT(PIPE_SHADER_TESS_CTRL); return true; } diff --git a/src/gallium/drivers/v3d/v3d_screen.c b/src/gallium/drivers/v3d/v3d_screen.c index 51aa25f85f6..76883e1c172 100644 --- a/src/gallium/drivers/v3d/v3d_screen.c +++ b/src/gallium/drivers/v3d/v3d_screen.c @@ -605,17 +605,6 @@ v3d_screen_get_compiler_options(struct pipe_screen *pscreen, .has_uclz = true, .divergence_analysis_options = nir_divergence_multiple_workgroup_per_compute_subgroup, - /* We don't currently support this in the backend, but that is - * okay because our NIR compiler sets the option - * lower_all_io_to_temps, which will eliminate indirect - * indexing on all input/output variables by translating it to - * indirect indexing on temporary variables instead, which we - * will then lower to scratch. We prefer this over setting this - * to 0, which would cause if-ladder injection to eliminate - * indirect indexing on inputs. - */ - .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), - .support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), /* This will enable loop unrolling in the state tracker so we won't * be able to selectively disable it in backend if it leads to * lower thread counts or TMU spills. Choose a conservative maximum to diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c index b57e0d5e74b..342aa4887ca 100644 --- a/src/gallium/drivers/virgl/virgl_screen.c +++ b/src/gallium/drivers/virgl/virgl_screen.c @@ -1085,7 +1085,7 @@ virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *c screen->compiler_options.lower_ldexp = true; screen->compiler_options.lower_image_offset_to_range_base = true; screen->compiler_options.lower_atomic_offset_to_range_base = true; - screen->compiler_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES); + screen->compiler_options.support_indirect_outputs = BITFIELD_BIT(PIPE_SHADER_TESS_CTRL); if (screen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR) { screen->compiler_options.support_indirect_inputs |= BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |