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i965: Eliminate brw->cs.prog_data pointer.

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Just say no to:

-   brw->cs.base.prog_data = &brw->cs.prog_data->base.base;

We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_cs_prog_data as needed.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
This commit is contained in:
Kenneth Graunke
2016-09-08 23:48:53 -07:00
parent 16d5536e55
commit a85a8ecd32
6 changed files with 18 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_compute.c
+2 -1
View File
@@ -115,7 +115,8 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
static void
brw_emit_gpgpu_walker(struct brw_context *brw)
{
const struct brw_cs_prog_data *prog_data = brw->cs.prog_data;
const struct brw_cs_prog_data *prog_data =
brw_cs_prog_data(brw->cs.base.prog_data);
const GLuint *num_groups = brw->compute.num_work_groups;
uint32_t indirect_flag;
src/mesa/drivers/dri/i965/brw_context.h
-1
View File
@@ -1195,7 +1195,6 @@ struct brw_context
struct {
struct brw_stage_state base;
struct brw_cs_prog_data *prog_data;
} cs;
/* RS hardware binding table */
src/mesa/drivers/dri/i965/brw_cs.c
+5 -5
View File
@@ -180,7 +180,7 @@ brw_codegen_cs_prog(struct brw_context *brw,
key, sizeof(*key),
program, program_size,
&prog_data, sizeof(prog_data),
&brw->cs.base.prog_offset, &brw->cs.prog_data);
&brw->cs.base.prog_offset, &brw->cs.base.prog_data);
ralloc_free(mem_ctx);
return true;
@@ -227,7 +227,8 @@ brw_upload_cs_prog(struct brw_context *brw)
if (!brw_search_cache(&brw->cache, BRW_CACHE_CS_PROG,
&key, sizeof(key),
&brw->cs.base.prog_offset, &brw->cs.prog_data)) {
&brw->cs.base.prog_offset,
&brw->cs.base.prog_data)) {
bool success =
brw_codegen_cs_prog(brw,
ctx->Shader.CurrentProgram[MESA_SHADER_COMPUTE],
@@ -235,7 +236,6 @@ brw_upload_cs_prog(struct brw_context *brw)
(void) success;
assert(success);
}
brw->cs.base.prog_data = &brw->cs.prog_data->base;
}
@@ -256,12 +256,12 @@ brw_cs_precompile(struct gl_context *ctx,
brw_setup_tex_for_precompile(brw, &key.tex, prog);
uint32_t old_prog_offset = brw->cs.base.prog_offset;
struct brw_cs_prog_data *old_prog_data = brw->cs.prog_data;
struct brw_stage_prog_data *old_prog_data = brw->cs.base.prog_data;
bool success = brw_codegen_cs_prog(brw, shader_prog, bcp, &key);
brw->cs.base.prog_offset = old_prog_offset;
brw->cs.prog_data = old_prog_data;
brw->cs.base.prog_data = old_prog_data;
return success;
}
src/mesa/drivers/dri/i965/brw_state_cache.c
-1
View File
@@ -403,7 +403,6 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache)
brw->tes.base.prog_data = NULL;
brw->gs.base.prog_data = NULL;
brw->wm.base.prog_data = NULL;
brw->cs.prog_data = NULL;
brw->cs.base.prog_data = NULL;
intel_batchbuffer_flush(brw);
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+5 -4
View File
@@ -1464,7 +1464,7 @@ brw_upload_cs_ubo_surfaces(struct brw_context *brw)
/* BRW_NEW_CS_PROG_DATA */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
&brw->cs.base, &brw->cs.prog_data->base);
&brw->cs.base, brw->cs.base.prog_data);
}
const struct brw_tracked_state brw_cs_ubo_surfaces = {
@@ -1542,7 +1542,7 @@ brw_upload_cs_abo_surfaces(struct brw_context *brw)
if (prog) {
/* BRW_NEW_CS_PROG_DATA */
brw_upload_abo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
&brw->cs.base, &brw->cs.prog_data->base);
&brw->cs.base, brw->cs.base.prog_data);
}
}
@@ -1568,7 +1568,7 @@ brw_upload_cs_image_surfaces(struct brw_context *brw)
if (prog) {
/* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
&brw->cs.base, &brw->cs.prog_data->base);
&brw->cs.base, brw->cs.base.prog_data);
}
}
@@ -1848,7 +1848,8 @@ brw_upload_cs_work_groups_surface(struct brw_context *brw)
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
/* BRW_NEW_CS_PROG_DATA */
const struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
const struct brw_cs_prog_data *cs_prog_data =
brw_cs_prog_data(brw->cs.base.prog_data);
if (prog && cs_prog_data->uses_num_work_groups) {
const unsigned surf_idx =
src/mesa/drivers/dri/i965/gen7_cs_state.c
+6 -5
View File
@@ -37,15 +37,15 @@
static void
brw_upload_cs_state(struct brw_context *brw)
{
if (!brw->cs.prog_data)
if (!brw->cs.base.prog_data)
return;
uint32_t offset;
uint32_t *desc = (uint32_t*) brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
8 * 4, 64, &offset);
struct brw_stage_state *stage_state = &brw->cs.base;
struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
struct brw_stage_prog_data *prog_data = stage_state->prog_data;
struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data);
const struct gen_device_info *devinfo = &brw->screen->devinfo;
if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
@@ -285,7 +285,8 @@ gen7_upload_cs_push_constants(struct brw_context *brw)
if (cp) {
/* BRW_NEW_CS_PROG_DATA */
struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
struct brw_cs_prog_data *cs_prog_data =
brw_cs_prog_data(brw->cs.base.prog_data);
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_COMPUTE);
brw_upload_cs_push_constants(brw, &cp->program.Base, cs_prog_data,
@@ -319,7 +320,7 @@ brw_upload_cs_pull_constants(struct brw_context *brw)
(struct brw_compute_program *) brw->compute_program;
/* BRW_NEW_CS_PROG_DATA */
const struct brw_stage_prog_data *prog_data = &brw->cs.prog_data->base;
const struct brw_stage_prog_data *prog_data = brw->cs.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_COMPUTE);
/* _NEW_PROGRAM_CONSTANTS */