From a82705911e13de3db9d38f09c6cb577602308930 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 7 Mar 2025 09:37:28 -0500 Subject: [PATCH] radeonsi: work around a primitive restart bug on gfx10-10.3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Using the GE instead of the VGT register has no effect because it's the same value. SQ_NON_EVENT is the fix. Discovered by Samuel Pitoiset. Cc: mesa-stable Acked-by: Pierre-Eric Pelloux-Prayer Tested-by: Dieter Nützel Part-of: --- src/gallium/drivers/radeonsi/si_state_draw.cpp | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index 3151ecc0cec..f80c1067896 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -1157,10 +1157,20 @@ static void si_emit_draw_registers(struct si_context *sctx, } } else { if (primitive_restart != sctx->last_primitive_restart_en) { - if (GFX_VERSION >= GFX9) + if (GFX_VERSION >= GFX10) { + /* GFX10-GFX10.3 (tested on NAVI10, NAVI21 and NAVI24 but likely all) are + * affected by a hw bug when primitive restart is updated and no context + * registers are written between draws. One workaround is to emit + * SQ_NON_EVENT(0) which is a NOP packet that adds a small delay and seems + * to fix it reliably. + */ + radeon_event_write(V_028A90_SQ_NON_EVENT); + radeon_set_uconfig_reg(R_03092C_GE_MULTI_PRIM_IB_RESET_EN, primitive_restart); + } else if (GFX_VERSION >= GFX9) { radeon_set_uconfig_reg(R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart); - else + } else { radeon_set_context_reg(R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart); + } sctx->last_primitive_restart_en = primitive_restart; } if (si_prim_restart_index_changed(sctx, index_size, primitive_restart,