From a80a1c983844bca646d5f07d65c695a84f964bfe Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 10 Jun 2024 12:11:53 +0200 Subject: [PATCH] radv: don't assume that TC_ACTION_ENA invalidates L1 cache on gfx9 Ported from RadeonSI 279315fd73e ("radeonsi: don't assume that TC_ACTION_ENA invalidates L1 cache on gfx9") Thanks to Rhys for noticing this by inspection. Cc: mesa-stable Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c index f760e3128cf..28b27a8b2f9 100644 --- a/src/amd/vulkan/radv_cs.c +++ b/src/amd/vulkan/radv_cs.c @@ -458,7 +458,7 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enu * All operations that invalidate L2 also seem to invalidate * metadata. Volatile (VOL) and WC flushes are not listed here. * - * TC | TC_WB = writeback & invalidate L2 & L1 + * TC | TC_WB = writeback & invalidate L2 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC * TC_WB | TC_NC = writeback L2 for MTYPE == NC * TC | TC_NC = invalidate L2 for MTYPE == NC @@ -471,11 +471,11 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enu /* Ideally flush TC together with CB/DB. */ if (flush_bits & RADV_CMD_FLAG_INV_L2) { - /* Writeback and invalidate everything in L2 & L1. */ + /* Writeback and invalidate everything in L2. */ tc_flags = EVENT_TC_ACTION_ENA | EVENT_TC_WB_ACTION_ENA; /* Clear the flags. */ - flush_bits &= ~(RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_WB_L2 | RADV_CMD_FLAG_INV_VCACHE); + flush_bits &= ~(RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_WB_L2); *sqtt_flush_bits |= RGP_FLUSH_INVAL_L2; }