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intel/fs/gen7+: Swap sample mask flag register and FIND_LIVE_CHANNEL temporary.

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FIND_LIVE_CHANNEL was using f1.0-f1.1 as temporary flag register on
Gen7, instead use f0.0-f0.1.  In order to avoid collision with the
discard sample mask, move the latter to f1.0-f1.1.  This makes room
for keeping track of the sample mask of the second half of SIMD32
programs that use discard.

Note that some MOVs of the sample mask into f1.0 become redundant now
in lower_surface_logical_send() and lower_a64_logical_send().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>x
This commit is contained in:
Francisco Jerez
2020-01-04 15:48:07 -08:00
parent 083fd96a97
commit a792e11f5c
4 changed files with 18 additions and 13 deletions
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src/intel/compiler/brw_fs.cpp
+10 -7
View File
@@ -5458,15 +5458,17 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
* vertical predication mode.
*/
inst->predicate = BRW_PREDICATE_ALIGN1_ALLV;
ubld.MOV(retype(brw_flag_subreg(inst->flag_subreg + 2),
sample_mask.type),
sample_mask);
if (sample_mask.file != ARF || sample_mask.nr != BRW_ARF_FLAG + 1)
ubld.MOV(retype(brw_flag_subreg(inst->flag_subreg + 2),
sample_mask.type),
sample_mask);
} else {
inst->flag_subreg = 2;
inst->predicate = BRW_PREDICATE_NORMAL;
inst->predicate_inverse = false;
ubld.MOV(retype(brw_flag_subreg(inst->flag_subreg), sample_mask.type),
sample_mask);
if (sample_mask.file != ARF || sample_mask.nr != BRW_ARF_FLAG + 1)
ubld.MOV(retype(brw_flag_subreg(inst->flag_subreg), sample_mask.type),
sample_mask);
}
}
@@ -5646,8 +5648,9 @@ lower_a64_logical_send(const fs_builder &bld, fs_inst *inst)
fs_reg sample_mask = sample_mask_reg(bld);
const fs_builder ubld = bld.group(1, 0).exec_all();
ubld.MOV(retype(brw_flag_subreg(inst->flag_subreg), sample_mask.type),
sample_mask);
if (sample_mask.file != ARF || sample_mask.nr != BRW_ARF_FLAG + 1)
ubld.MOV(retype(brw_flag_subreg(inst->flag_subreg), sample_mask.type),
sample_mask);
}
fs_reg payload, payload2;