diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 139f4954dfa..6d9cce2619b 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1088,7 +1088,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
 	}
 
 	sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
-	assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
 	sscreen->tess_offchip_ring_size = max_offchip_buffers *
 					  sscreen->tess_offchip_block_dw_size * 4;
 
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 65035f0e256..032d7a09cc4 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -3725,6 +3725,7 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
 static void si_init_tess_factor_ring(struct si_context *sctx)
 {
 	assert(!sctx->tess_rings);
+	assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
 
 	/* The address must be aligned to 2^19, because the shader only
 	 * receives the high 13 bits.