From a60181e8f2ed755950cfcaf732e834ceb6cd7a89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 8 Aug 2022 03:27:28 -0400 Subject: [PATCH] radeonsi: use do..while loops and other cosmetic changes in display list path Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- .../drivers/radeonsi/si_state_draw.cpp | 25 +++++++++---------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index dc479123e26..9fda376f57c 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -1946,21 +1946,21 @@ static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx, offset, alloc_size); } - if (IS_DRAW_VERTEX_STATE) { - unsigned i = 0; + unsigned count_in_user_sgprs = MIN2(count, num_vbos_in_user_sgprs); + unsigned i = 0; + if (IS_DRAW_VERTEX_STATE) { radeon_begin(&sctx->gfx_cs); - if (num_vbos_in_user_sgprs) { - unsigned num_vb_sgprs = MIN2(count, num_vbos_in_user_sgprs) * 4; + if (count_in_user_sgprs) { + radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, count_in_user_sgprs * 4); - radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_vb_sgprs); - - for (; partial_velem_mask && i < num_vbos_in_user_sgprs; i++) { + /* the first iteration always executes */ + do { unsigned velem_index = get_next_vertex_state_elem(state, &partial_velem_mask); radeon_emit_array(&vstate->descriptors[velem_index * 4], 4); - } + } while (++i < count_in_user_sgprs); } if (partial_velem_mask) { @@ -1971,12 +1971,14 @@ static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx, radeon_set_sh_reg(vb_desc_offset, vb_descriptors_address); - for (; partial_velem_mask; i++) { + /* the first iteration always executes */ + do { unsigned velem_index = get_next_vertex_state_elem(state, &partial_velem_mask); uint32_t *desc = &ptr[(i - num_vbos_in_user_sgprs) * 4]; memcpy(desc, &vstate->descriptors[velem_index * 4], 16); - } + i++; + } while (partial_velem_mask); } radeon_end(); @@ -1989,9 +1991,6 @@ static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx, /* The next draw_vbo should recompute and rebind vertex buffer descriptors. */ sctx->vertex_buffers_dirty = sctx->num_vertex_elements > 0; } else { - unsigned count_in_user_sgprs = MIN2(count, num_vbos_in_user_sgprs); - unsigned i = 0; - if (count_in_user_sgprs) { radeon_begin(&sctx->gfx_cs); radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4,