From a47184e3962200dba7a84aa9382df4129cf132fe Mon Sep 17 00:00:00 2001 From: Faith Ekstrand Date: Fri, 10 Oct 2025 17:08:27 -0400 Subject: [PATCH] util/cache_ops/x86: Call util_get_cpu_caps() less This also makes all the paths a bit more clear because we only ever clflushopt on the clflusopt paths and only ever clflush on the clflush paths. It's really not much more code or logic duplication. Reviewed-by: Lionel Landwerlin Part-of: --- src/util/cache_ops_x86.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/util/cache_ops_x86.c b/src/util/cache_ops_x86.c index 370296cc3b2..d8d748d9ec4 100644 --- a/src/util/cache_ops_x86.c +++ b/src/util/cache_ops_x86.c @@ -66,12 +66,16 @@ void util_flush_range(void *start, size_t size) { __builtin_ia32_mfence(); - util_clflush_range(start, size); #ifdef HAVE___BUILTIN_IA32_CLFLUSHOPT - /* clflushopt doesn't include an mfence like clflush */ - if (util_get_cpu_caps()->has_clflushopt) + if (util_get_cpu_caps()->has_clflushopt) { + util_clflushopt_range(start, size); + /* clflushopt doesn't include an mfence like clflush */ __builtin_ia32_mfence(); + return; + } #endif + util_clflush_range(start, size); + /* The last clflush acts as an mfence */ } void @@ -80,8 +84,6 @@ util_flush_inval_range_no_fence(void *start, size_t size) if (size == 0) return; - util_flush_range_no_fence(start, size); - /* Modern Atom CPUs (Baytrail+) have issues with clflush serialization, * where mfence is not a sufficient synchronization barrier. We must * double clflush the last cacheline. This guarantees it will be ordered @@ -94,12 +96,14 @@ util_flush_inval_range_no_fence(void *start, size_t size) */ #ifdef HAVE___BUILTIN_IA32_CLFLUSHOPT if (util_get_cpu_caps()->has_clflushopt) { + util_clflushopt_range(start, size); /* clflushopt doesn't include an mfence like clflush */ __builtin_ia32_mfence(); util_clflushopt_range((char *)start + size - 1, 1); return; } #endif + util_clflush_range(start, size); __builtin_ia32_clflush((char *)start + size - 1); }