From a46e8304446b7c1a0673ad1634139541bb82d240 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Wed, 9 Dec 2020 10:38:34 +0100 Subject: [PATCH] radeonsi: add radeon_set_uconfig_reg_seq_perfctr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák Part-of: --- src/gallium/drivers/radeonsi/si_build_pm4.h | 12 +++++++++--- src/gallium/drivers/radeonsi/si_compute.c | 2 +- .../drivers/radeonsi/si_compute_prim_discard.c | 2 +- src/gallium/drivers/radeonsi/si_perfcounter.c | 14 +++++++------- 4 files changed, 18 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h index b1fd406332a..0294c455fb2 100644 --- a/src/gallium/drivers/radeonsi/si_build_pm4.h +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h @@ -102,18 +102,24 @@ static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, uns radeon_emit(cs, value); } -static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) +static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num, bool perfctr) { SI_CHECK_SHADOWED_REGS(reg, num); assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); - radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); + radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, perfctr)); radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); } static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { - radeon_set_uconfig_reg_seq(cs, reg, 1); + radeon_set_uconfig_reg_seq(cs, reg, 1, false); + radeon_emit(cs, value); +} + +static inline void radeon_set_uconfig_reg_perfctr(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) +{ + radeon_set_uconfig_reg_seq(cs, reg, 1, true); radeon_emit(cs, value); } diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 775d92421f2..a0213015406 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -382,7 +382,7 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf } /* Set the pointer to border colors. */ - radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2); + radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2, false); radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */ radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */ } diff --git a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c index 159bd852aed..10e46687de1 100644 --- a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c +++ b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c @@ -1226,7 +1226,7 @@ void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx, /* Disable ordered alloc for OA resources. */ for (unsigned i = 0; i < 2; i++) { - radeon_set_uconfig_reg_seq(cs, R_031074_GDS_OA_CNTL, 3); + radeon_set_uconfig_reg_seq(cs, R_031074_GDS_OA_CNTL, 3, false); radeon_emit(cs, S_031074_INDEX(i)); radeon_emit(cs, 0); radeon_emit(cs, S_03107C_ENABLE(0)); diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c index 1f2605ee648..f28a51ffd52 100644 --- a/src/gallium/drivers/radeonsi/si_perfcounter.c +++ b/src/gallium/drivers/radeonsi/si_perfcounter.c @@ -730,7 +730,7 @@ static void si_pc_emit_shaders(struct si_context *sctx, unsigned shaders) { struct radeon_cmdbuf *cs = &sctx->gfx_cs; - radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2); + radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2, false); radeon_emit(cs, shaders & 0x7f); radeon_emit(cs, 0xffffffff); } @@ -755,7 +755,7 @@ static void si_pc_emit_select(struct si_context *sctx, struct si_pc_block *block dw = count + regs->num_prelude; if (count >= regs->num_multi) dw += regs->num_multi; - radeon_set_uconfig_reg_seq(cs, regs->select0, dw); + radeon_set_uconfig_reg_seq(cs, regs->select0, dw, false); for (idx = 0; idx < regs->num_prelude; ++idx) radeon_emit(cs, 0); for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx) @@ -763,7 +763,7 @@ static void si_pc_emit_select(struct si_context *sctx, struct si_pc_block *block if (count < regs->num_multi) { unsigned select1 = regs->select0 + 4 * regs->num_multi; - radeon_set_uconfig_reg_seq(cs, select1, count); + radeon_set_uconfig_reg_seq(cs, select1, count, false); } for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx) @@ -778,7 +778,7 @@ static void si_pc_emit_select(struct si_context *sctx, struct si_pc_block *block assert(!(regs->layout & SI_PC_REG_REVERSE)); - radeon_set_uconfig_reg_seq(cs, regs->select0, count + regs->num_prelude); + radeon_set_uconfig_reg_seq(cs, regs->select0, count + regs->num_prelude, false); for (idx = 0; idx < regs->num_prelude; ++idx) radeon_emit(cs, 0); for (idx = 0; idx < count; ++idx) @@ -786,7 +786,7 @@ static void si_pc_emit_select(struct si_context *sctx, struct si_pc_block *block select1 = regs->select0 + 4 * regs->num_counters; select1_count = MIN2(count, regs->num_multi); - radeon_set_uconfig_reg_seq(cs, select1, select1_count); + radeon_set_uconfig_reg_seq(cs, select1, select1_count, false); for (idx = 0; idx < select1_count; ++idx) radeon_emit(cs, 0); } else if (layout_multi == SI_PC_MULTI_CUSTOM) { @@ -804,7 +804,7 @@ static void si_pc_emit_select(struct si_context *sctx, struct si_pc_block *block reg_count += regs->num_prelude; if (!(regs->layout & SI_PC_REG_REVERSE)) { - radeon_set_uconfig_reg_seq(cs, reg_base, reg_count); + radeon_set_uconfig_reg_seq(cs, reg_base, reg_count, false); for (idx = 0; idx < regs->num_prelude; ++idx) radeon_emit(cs, 0); @@ -815,7 +815,7 @@ static void si_pc_emit_select(struct si_context *sctx, struct si_pc_block *block } } else { reg_base -= (reg_count - 1) * 4; - radeon_set_uconfig_reg_seq(cs, reg_base, reg_count); + radeon_set_uconfig_reg_seq(cs, reg_base, reg_count, false); for (idx = count; idx > 0; --idx) { if (idx <= regs->num_multi)