From a42c57dc0131705be10b5641e3d4592722f17c78 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sat, 18 Feb 2023 13:45:22 +0100 Subject: [PATCH] aco: Always enable idxen for swizzled buffer access on GFX11. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This helps pass the mesh shader I/O tests. Swizzled buffer addressing seems to be broken on GFX11 when the idxen bit is 0. No Fossil DB changes on Rembrandt (GFX10.3). Signed-off-by: Timur Kristóf Reviewed-by: Rhys Perry Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 121ca1841b9..66eeccc575e 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -7038,7 +7038,10 @@ visit_load_buffer(isel_context* ctx, nir_intrinsic_instr* intrin) { Builder bld(ctx->program, ctx->block); - bool idxen = !nir_src_is_const(intrin->src[3]) || nir_src_as_uint(intrin->src[3]); + /* Swizzled buffer addressing seems to be broken on GFX11 without the idxen bit. */ + bool swizzled = nir_intrinsic_access(intrin) & ACCESS_IS_SWIZZLED_AMD; + bool idxen = (swizzled && ctx->program->gfx_level >= GFX11) || + !nir_src_is_const(intrin->src[3]) || nir_src_as_uint(intrin->src[3]); bool v_offset_zero = nir_src_is_const(intrin->src[1]) && !nir_src_as_uint(intrin->src[1]); bool s_offset_zero = nir_src_is_const(intrin->src[2]) && !nir_src_as_uint(intrin->src[2]); @@ -7050,7 +7053,6 @@ visit_load_buffer(isel_context* ctx, nir_intrinsic_instr* intrin) s_offset_zero ? Temp(0, s1) : bld.as_uniform(get_ssa_temp(ctx, intrin->src[2].ssa)); Temp idx = idxen ? as_vgpr(ctx, get_ssa_temp(ctx, intrin->src[3].ssa)) : Temp(); - bool swizzled = nir_intrinsic_access(intrin) & ACCESS_IS_SWIZZLED_AMD; bool glc = nir_intrinsic_access(intrin) & ACCESS_COHERENT; bool slc = nir_intrinsic_access(intrin) & ACCESS_STREAM_CACHE_POLICY; @@ -7108,7 +7110,10 @@ visit_store_buffer(isel_context* ctx, nir_intrinsic_instr* intrin) { Builder bld(ctx->program, ctx->block); - bool idxen = !nir_src_is_const(intrin->src[4]) || nir_src_as_uint(intrin->src[4]); + /* Swizzled buffer addressing seems to be broken on GFX11 without the idxen bit. */ + bool swizzled = nir_intrinsic_access(intrin) & ACCESS_IS_SWIZZLED_AMD; + bool idxen = (swizzled && ctx->program->gfx_level >= GFX11) || + !nir_src_is_const(intrin->src[4]) || nir_src_as_uint(intrin->src[4]); bool v_offset_zero = nir_src_is_const(intrin->src[2]) && !nir_src_as_uint(intrin->src[2]); bool s_offset_zero = nir_src_is_const(intrin->src[3]) && !nir_src_as_uint(intrin->src[3]); @@ -7120,7 +7125,6 @@ visit_store_buffer(isel_context* ctx, nir_intrinsic_instr* intrin) s_offset_zero ? Temp(0, s1) : bld.as_uniform(get_ssa_temp(ctx, intrin->src[3].ssa)); Temp idx = idxen ? as_vgpr(ctx, get_ssa_temp(ctx, intrin->src[4].ssa)) : Temp(); - bool swizzled = nir_intrinsic_access(intrin) & ACCESS_IS_SWIZZLED_AMD; bool glc = nir_intrinsic_access(intrin) & ACCESS_COHERENT; bool slc = nir_intrinsic_access(intrin) & ACCESS_STREAM_CACHE_POLICY;