ac/nir/ngg: Add and use a has_ngg_fully_culled_bug field to ac_gpu_info.

Better than applying the workaround ad-hoc based on GFX level.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>

src/amd/common/ac_gpu_info.c

@@ -1300,6 +1300,11 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
    info->has_taskmesh_indirect0_bug = info->gfx_level == GFX10_3 &&
                                       info->mec_fw_version < 100;
 
+   /* Some GFX10 chips can hang when NGG exports zero vertices and primitives.
+    * The workaround is to always export a single degenerate triangle.
+    */
+   info->has_ngg_fully_culled_bug = info->gfx_level == GFX10;
+
    info->has_export_conflict_bug = info->gfx_level == GFX11;
 
    /* The hw starts culling after all exports are finished,

src/amd/common/ac_gpu_info.h

@@ -115,6 +115,7 @@ struct radeon_info {
    bool has_sqtt_auto_flush_mode_bug;
    bool never_send_perfcounter_stop;
    bool discardable_allows_big_page;
+   bool has_ngg_fully_culled_bug;
    bool has_export_conflict_bug;
    bool has_attr_ring_wait_bug;
    bool has_vrs_ds_export_bug;

src/amd/common/nir/ac_nir_lower_ngg.c

@@ -1355,7 +1355,7 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c
 
       nir_if *if_wave_0 = nir_push_if(b, nir_ieq_imm(b, nir_load_subgroup_id(b), 0));
       {
-         ac_nir_ngg_alloc_vertices_and_primitives(b, num_live_vertices_in_workgroup, num_exported_prims, s->options->gfx_level == GFX10);
+         ac_nir_ngg_alloc_vertices_and_primitives(b, num_live_vertices_in_workgroup, num_exported_prims, s->options->hw_info->has_ngg_fully_culled_bug);
       }
       nir_pop_if(b, if_wave_0);
 
@@ -2721,7 +2721,7 @@ ngg_gs_finale(nir_builder *b, lower_ngg_gs_state *s)
 
          ac_nir_ngg_alloc_vertices_and_primitives(b, max_vtxcnt, max_prmcnt,
                                                   b->shader->info.gs.vertices_out == 0 &&
-                                                  s->options->gfx_level == GFX10);
+                                                  s->options->hw_info->has_ngg_fully_culled_bug);
       }
       nir_pop_if(b, if_wave_0);
    }
@@ -2771,7 +2771,7 @@ ngg_gs_finale(nir_builder *b, lower_ngg_gs_state *s)
    /* Allocate export space. We currently don't compact primitives, just use the maximum number. */
    nir_if *if_wave_0 = nir_push_if(b, nir_ieq_imm(b, nir_load_subgroup_id(b), 0));
    {
-      ac_nir_ngg_alloc_vertices_and_primitives(b, workgroup_num_vertices, max_prmcnt, s->options->gfx_level == GFX10);
+      ac_nir_ngg_alloc_vertices_and_primitives(b, workgroup_num_vertices, max_prmcnt, s->options->hw_info->has_ngg_fully_culled_bug);
    }
    nir_pop_if(b, if_wave_0);
 

src/amd/vulkan/winsys/null/radv_null_winsys.c

@@ -119,6 +119,7 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *gpu_i
    gpu_info->has_image_opcodes = true;
    gpu_info->has_attr_ring = gpu_info->gfx_level >= GFX11;
    gpu_info->has_attr_ring_wait_bug = gpu_info->gfx_level == GFX11 || gpu_info->gfx_level == GFX11_5;
+   gpu_info->has_ngg_fully_culled_bug = gpu_info->gfx_level == GFX10;
 
    if (gpu_info->family == CHIP_NAVI31 || gpu_info->family == CHIP_NAVI32)
       gpu_info->num_physical_wave64_vgprs_per_simd = 768;