From a33b9d43d846a4e87aff4915e15146e0071c9bd8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Fri, 13 May 2022 12:06:49 +0200 Subject: [PATCH] aco: add RT stage enums Part-of: --- .../aco_instruction_selection_setup.cpp | 16 +++++++++++++++- src/amd/compiler/aco_ir.h | 19 +++++++++++-------- src/amd/compiler/aco_print_ir.cpp | 2 ++ 3 files changed, 28 insertions(+), 9 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index cb2d5e27350..78c0ac3a5e4 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -306,7 +306,13 @@ setup_variables(isel_context* ctx, nir_shader* nir) break; } case MESA_SHADER_COMPUTE: - case MESA_SHADER_TASK: { + case MESA_SHADER_TASK: + case MESA_SHADER_RAYGEN: + case MESA_SHADER_CLOSEST_HIT: + case MESA_SHADER_MISS: + case MESA_SHADER_CALLABLE: + case MESA_SHADER_INTERSECTION: + case MESA_SHADER_ANY_HIT: { ctx->program->config->lds_size = DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule); break; @@ -774,6 +780,12 @@ setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* c case MESA_SHADER_COMPUTE: sw_stage = sw_stage | SWStage::CS; break; case MESA_SHADER_TASK: sw_stage = sw_stage | SWStage::TS; break; case MESA_SHADER_MESH: sw_stage = sw_stage | SWStage::MS; break; + case MESA_SHADER_RAYGEN: + case MESA_SHADER_CLOSEST_HIT: + case MESA_SHADER_MISS: + case MESA_SHADER_CALLABLE: + case MESA_SHADER_INTERSECTION: + case MESA_SHADER_ANY_HIT: sw_stage = SWStage::RT; break; default: unreachable("Shader stage not implemented"); } } @@ -822,6 +834,8 @@ setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* c hw_stage = HWStage::GS; /* GFX9: TES+GS merged into a GS (and GFX10/legacy) */ else if (sw_stage == SWStage::TES_GS && ngg) hw_stage = HWStage::NGG; /* GFX10+: TES+GS merged into an NGG GS */ + else if (sw_stage == SWStage::RT) + hw_stage = HWStage::CS; /* Raytracing shaders run as CS */ else unreachable("Shader stage not implemented"); diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index b7a8a8f3fce..5045fdef001 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -1945,14 +1945,15 @@ struct Block { */ enum class SWStage : uint16_t { None = 0, - VS = 1 << 0, /* Vertex Shader */ - GS = 1 << 1, /* Geometry Shader */ - TCS = 1 << 2, /* Tessellation Control aka Hull Shader */ - TES = 1 << 3, /* Tessellation Evaluation aka Domain Shader */ - FS = 1 << 4, /* Fragment aka Pixel Shader */ - CS = 1 << 5, /* Compute Shader */ - TS = 1 << 6, /* Task Shader */ - MS = 1 << 7, /* Mesh Shader */ + VS = 1 << 0, /* Vertex Shader */ + GS = 1 << 1, /* Geometry Shader */ + TCS = 1 << 2, /* Tessellation Control aka Hull Shader */ + TES = 1 << 3, /* Tessellation Evaluation aka Domain Shader */ + FS = 1 << 4, /* Fragment aka Pixel Shader */ + CS = 1 << 5, /* Compute Shader */ + TS = 1 << 6, /* Task Shader */ + MS = 1 << 7, /* Mesh Shader */ + RT = 1 << 8, /* Raytracing Shader */ /* Stage combinations merged to run on a single HWStage */ VS_GS = VS | GS, @@ -2036,6 +2037,8 @@ static constexpr Stage tess_control_hs(HWStage::HS, SWStage::TCS); static constexpr Stage tess_eval_es(HWStage::ES, SWStage::TES); /* tesselation evaluation before geometry */ static constexpr Stage geometry_gs(HWStage::GS, SWStage::GS); +/* Raytracing */ +static constexpr Stage raytracing_cs(HWStage::CS, SWStage::RT); struct DeviceInfo { uint16_t lds_encoding_granule; diff --git a/src/amd/compiler/aco_print_ir.cpp b/src/amd/compiler/aco_print_ir.cpp index 6d2dab9b29b..d5e24b18bfa 100644 --- a/src/amd/compiler/aco_print_ir.cpp +++ b/src/amd/compiler/aco_print_ir.cpp @@ -868,6 +868,8 @@ print_stage(Stage stage, FILE* output) fprintf(output, "mesh_ngg"); else if (stage == task_cs) fprintf(output, "task_cs"); + else if (stage == raytracing_cs) + fprintf(output, "raytracing_cs"); else fprintf(output, "unknown");