From a338a2da588703ad26ddc78611f9698bd1398499 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Fri, 21 Oct 2022 15:03:22 -0400
Subject: [PATCH] amd/registers: regenerate gfx11 headers from
 amd-staging-drm-next

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19419>
---
 src/amd/registers/gfx11.json | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/src/amd/registers/gfx11.json b/src/amd/registers/gfx11.json
index 38308f06641..088b3a221ca 100644
--- a/src/amd/registers/gfx11.json
+++ b/src/amd/registers/gfx11.json
@@ -2366,6 +2366,12 @@
    "name": "GL1C_STATUS",
    "type_ref": "GL1C_STATUS"
   },
+  {
+   "chips": ["gfx11"],
+   "map": {"at": 46344, "to": "mm"},
+   "name": "GL1C_UTCL0_CNTL1",
+   "type_ref": "GL1C_UTCL0_CNTL1"
+  },
   {
    "chips": ["gfx11"],
    "map": {"at": 46348, "to": "mm"},
@@ -12464,6 +12470,22 @@
     {"bits": [31, 31], "name": "TRACKER_LAST_SET_MATCHES_CURRENT_SET"}
    ]
   },
+  "GL1C_UTCL0_CNTL1": {
+   "fields": [
+    {"bits": [0, 0], "name": "FORCE_4K_L2_RESP"},
+    {"bits": [1, 1], "name": "GPUVM_64K_DEF"},
+    {"bits": [2, 2], "name": "GPUVM_PERM_MODE"},
+    {"bits": [3, 4], "name": "RESP_MODE"},
+    {"bits": [5, 6], "name": "RESP_FAULT_MODE"},
+    {"bits": [7, 15], "name": "CLIENTID"},
+    {"bits": [19, 22], "name": "REG_INV_VMID"},
+    {"bits": [24, 24], "name": "REG_INV_TOGGLE"},
+    {"bits": [26, 26], "name": "FORCE_MISS"},
+    {"bits": [27, 28], "name": "FORCE_IN_ORDER"},
+    {"bits": [28, 29], "name": "REDUCE_FIFO_DEPTH_BY_2"},
+    {"bits": [30, 31], "name": "REDUCE_CACHE_SIZE_BY_2"}
+   ]
+  },
   "GL1C_UTCL0_CNTL2": {
    "fields": [
     {"bits": [0, 7], "name": "SPARE"},