From a313d5f82a5c65fd5f676c57c92f663546fb314b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 4 Apr 2024 00:11:37 +0200 Subject: [PATCH] radv: Remove unused gfx_level from gfx10_emit_ge_pc_alloc. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_pipeline_graphics.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 92698c4fb7c..24b69730c07 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1127,7 +1127,7 @@ radv_pipeline_init_dynamic_state(const struct radv_device *device, struct radv_g } static void -gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t oversub_pc_lines) +gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, uint32_t oversub_pc_lines) { radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, S_030980_OVERSUB_EN(oversub_pc_lines > 0) | S_030980_NUM_PC_LINES(oversub_pc_lines - 1)); @@ -2951,7 +2951,7 @@ radv_emit_hw_vs(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, } if (pdev->info.gfx_level >= GFX10) { uint32_t oversub_pc_lines = late_alloc_wave64 ? pdev->info.pc_lines / 4 : 0; - gfx10_emit_ge_pc_alloc(cs, pdev->info.gfx_level, oversub_pc_lines); + gfx10_emit_ge_pc_alloc(cs, oversub_pc_lines); /* Required programming for tessellation (legacy pipeline only). */ if (shader->info.stage == MESA_SHADER_TESS_EVAL) { @@ -3139,7 +3139,7 @@ radv_emit_hw_ngg(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs, oversub_pc_lines *= oversub_factor; } - gfx10_emit_ge_pc_alloc(cs, pdev->info.gfx_level, oversub_pc_lines); + gfx10_emit_ge_pc_alloc(cs, oversub_pc_lines); } static void