From a1e694a890e5d1b3ace7a76cbdc31069d5081e2b Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Fri, 16 Feb 2024 14:19:13 -0800 Subject: [PATCH] intel/brw: Remove Gfx8- code from NIR passes Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_nir.c | 121 +++----- src/intel/compiler/brw_nir.h | 44 --- .../brw_nir_analyze_boolean_resolves.c | 258 ------------------ src/intel/compiler/meson.build | 1 - 4 files changed, 35 insertions(+), 389 deletions(-) delete mode 100644 src/intel/compiler/brw_nir_analyze_boolean_resolves.c diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index af691f26aac..1e8af6c89c3 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -23,12 +23,9 @@ #include "intel_nir.h" #include "brw_nir.h" -#include "brw_nir_rt.h" #include "brw_shader.h" -#include "dev/intel_debug.h" #include "compiler/glsl_types.h" #include "compiler/nir/nir_builder.h" -#include "util/u_math.h" /* * Returns the minimum number of vec4 (as_vec4 == true) or dvec4 (as_vec4 == @@ -622,15 +619,6 @@ brw_nir_lower_fs_inputs(nir_shader *nir, var->data.interpolation = flat ? INTERP_MODE_FLAT : INTERP_MODE_SMOOTH; } - - /* On Ironlake and below, there is only one interpolation mode. - * Centroid interpolation doesn't mean anything on this hardware -- - * there is no multisampling. - */ - if (devinfo->ver < 6) { - var->data.centroid = false; - var->data.sample = false; - } } nir_lower_io(nir, nir_var_shader_in, type_size_vec4, @@ -779,17 +767,13 @@ brw_nir_optimize(nir_shader *nir, * low. Therefore there shouldn't be a performance benefit to avoid it. */ OPT(nir_opt_peephole_select, 0, true, false); - OPT(nir_opt_peephole_select, 8, true, devinfo->ver >= 6); + OPT(nir_opt_peephole_select, 8, true, true); OPT(nir_opt_intrinsics); OPT(nir_opt_idiv_const, 32); OPT(nir_opt_algebraic); - /* BFI2 did not exist until Gfx7, so there's no point in trying to - * optimize an instruction that should not get generated. - */ - if (devinfo->ver >= 7) - OPT(nir_opt_reassociate_bfi); + OPT(nir_opt_reassociate_bfi); OPT(nir_lower_constant_convert_alu_types); OPT(nir_opt_constant_folding); @@ -836,9 +820,6 @@ brw_nir_optimize(nir_shader *nir, static unsigned lower_bit_size_callback(const nir_instr *instr, UNUSED void *data) { - const struct brw_compiler *compiler = (const struct brw_compiler *) data; - const struct intel_device_info *devinfo = compiler->devinfo; - switch (instr->type) { case nir_instr_type_alu: { nir_alu_instr *alu = nir_instr_as_alu(instr); @@ -884,7 +865,7 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data) case nir_op_flog2: case nir_op_fsin: case nir_op_fcos: - return devinfo->ver < 9 ? 32 : 0; + return 0; case nir_op_isign: assert(!"Should have been lowered by nir_opt_algebraic."); return 0; @@ -1582,30 +1563,23 @@ brw_vectorize_lower_mem_access(nir_shader *nir, OPT(nir_opt_load_store_vectorize, &options); - /* Only run the blockify optimization on Gfx9+ because although prior HW - * versions have support for block loads, they do have limitations on - * alignment as well as requiring split sends which are not supported - * there. - */ - if (compiler->devinfo->ver >= 9) { - /* Required for nir_divergence_analysis() */ - OPT(nir_convert_to_lcssa, true, true); + /* Required for nir_divergence_analysis() */ + OPT(nir_convert_to_lcssa, true, true); - /* When HW supports block loads, using the divergence analysis, try - * to find uniform SSBO loads and turn them into block loads. - * - * Rerun the vectorizer after that to make the largest possible block - * loads. - * - * This is a win on 2 fronts : - * - fewer send messages - * - reduced register pressure - */ - nir_divergence_analysis(nir); - if (OPT(intel_nir_blockify_uniform_loads, compiler->devinfo)) - OPT(nir_opt_load_store_vectorize, &options); - OPT(nir_opt_remove_phis); - } + /* When HW supports block loads, using the divergence analysis, try + * to find uniform SSBO loads and turn them into block loads. + * + * Rerun the vectorizer after that to make the largest possible block + * loads. + * + * This is a win on 2 fronts : + * - fewer send messages + * - reduced register pressure + */ + nir_divergence_analysis(nir); + if (OPT(intel_nir_blockify_uniform_loads, compiler->devinfo)) + OPT(nir_opt_load_store_vectorize, &options); + OPT(nir_opt_remove_phis); nir_lower_mem_access_bit_sizes_options mem_access_options = { .modes = nir_var_mem_ssbo | @@ -1696,21 +1670,19 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, if (OPT(nir_lower_int64)) brw_nir_optimize(nir, devinfo); - if (devinfo->ver >= 6) { - /* Try and fuse multiply-adds, if successful, run shrink_vectors to - * avoid peephole_ffma to generate things like this : - * vec16 ssa_0 = ... - * vec16 ssa_1 = fneg ssa_0 - * vec1 ssa_2 = ffma ssa_1, ... - * - * We want this instead : - * vec16 ssa_0 = ... - * vec1 ssa_1 = fneg ssa_0.x - * vec1 ssa_2 = ffma ssa_1, ... - */ - if (OPT(intel_nir_opt_peephole_ffma)) - OPT(nir_opt_shrink_vectors); - } + /* Try and fuse multiply-adds, if successful, run shrink_vectors to + * avoid peephole_ffma to generate things like this : + * vec16 ssa_0 = ... + * vec16 ssa_1 = fneg ssa_0 + * vec1 ssa_2 = ffma ssa_1, ... + * + * We want this instead : + * vec16 ssa_0 = ... + * vec1 ssa_1 = fneg ssa_0.x + * vec1 ssa_2 = ffma ssa_1, ... + */ + if (OPT(intel_nir_opt_peephole_ffma)) + OPT(nir_opt_shrink_vectors); OPT(intel_nir_opt_peephole_imul32x16); @@ -1725,7 +1697,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, * might be under the threshold of conversion to bcsel. */ OPT(nir_opt_peephole_select, 0, false, false); - OPT(nir_opt_peephole_select, 1, false, compiler->devinfo->ver >= 6); + OPT(nir_opt_peephole_select, 1, false, true); } do { @@ -1853,14 +1825,6 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, nir_trivialize_registers(nir); - /* This is the last pass we run before we start emitting stuff. It - * determines when we need to insert boolean resolves on Gen <= 5. We - * run it last because it stashes data in instr->pass_flags and we don't - * want that to be squashed by other NIR passes. - */ - if (devinfo->ver <= 5) - brw_nir_analyze_boolean_resolves(nir); - nir_sweep(nir); if (unlikely(debug_enabled)) { @@ -1875,7 +1839,6 @@ brw_nir_apply_sampler_key(nir_shader *nir, const struct brw_compiler *compiler, const struct brw_sampler_prog_key_data *key_tex) { - const struct intel_device_info *devinfo = compiler->devinfo; nir_lower_tex_options tex_options = { .lower_txd_clamp_bindless_sampler = true, .lower_txd_clamp_if_sampler_index_not_lt_16 = true, @@ -1883,20 +1846,6 @@ brw_nir_apply_sampler_key(nir_shader *nir, .lower_index_to_offset = true, }; - /* Iron Lake and prior require lowering of all rectangle textures */ - if (devinfo->ver < 6) - tex_options.lower_rect = true; - - /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */ - if (devinfo->ver < 8) { - tex_options.saturate_s = key_tex->gl_clamp_mask[0]; - tex_options.saturate_t = key_tex->gl_clamp_mask[1]; - tex_options.saturate_r = key_tex->gl_clamp_mask[2]; - } - - /* Prior to Haswell, we have to lower gradients on shadow samplers */ - tex_options.lower_txd_shadow = devinfo->verx10 <= 70; - return nir_lower_tex(nir, &tex_options); } @@ -2111,9 +2060,9 @@ brw_type_for_nir_type(const struct intel_device_info *devinfo, case nir_type_float64: return BRW_REGISTER_TYPE_DF; case nir_type_int64: - return devinfo->ver < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_Q; + return BRW_REGISTER_TYPE_Q; case nir_type_uint64: - return devinfo->ver < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_UQ; + return BRW_REGISTER_TYPE_UQ; case nir_type_int16: return BRW_REGISTER_TYPE_W; case nir_type_uint16: diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h index 36c249ac81f..ba9cf1cc23b 100644 --- a/src/intel/compiler/brw_nir.h +++ b/src/intel/compiler/brw_nir.h @@ -50,50 +50,6 @@ type_size_vec4_bytes(const struct glsl_type *type, bool bindless) return type_size_vec4(type, bindless) * 16; } -/* Flags set in the instr->pass_flags field by i965 analysis passes */ -enum { - BRW_NIR_NON_BOOLEAN = 0x0, - - /* Indicates that the given instruction's destination is a boolean - * value but that it needs to be resolved before it can be used. - * On Gen <= 5, CMP instructions return a 32-bit value where the bottom - * bit represents the actual true/false value of the compare and the top - * 31 bits are undefined. In order to use this value, we have to do a - * "resolve" operation by replacing the value of the CMP with -(x & 1) - * to sign-extend the bottom bit to 0/~0. - */ - BRW_NIR_BOOLEAN_NEEDS_RESOLVE = 0x1, - - /* Indicates that the given instruction's destination is a boolean - * value that has intentionally been left unresolved. Not all boolean - * values need to be resolved immediately. For instance, if we have - * - * CMP r1 r2 r3 - * CMP r4 r5 r6 - * AND r7 r1 r4 - * - * We don't have to resolve the result of the two CMP instructions - * immediately because the AND still does an AND of the bottom bits. - * Instead, we can save ourselves instructions by delaying the resolve - * until after the AND. The result of the two CMP instructions is left - * as BRW_NIR_BOOLEAN_UNRESOLVED. - */ - BRW_NIR_BOOLEAN_UNRESOLVED = 0x2, - - /* Indicates a that the given instruction's destination is a boolean - * value that does not need a resolve. For instance, if you AND two - * values that are BRW_NIR_BOOLEAN_NEEDS_RESOLVE then we know that both - * values will be 0/~0 before we get them and the result of the AND is - * also guaranteed to be 0/~0 and does not need a resolve. - */ - BRW_NIR_BOOLEAN_NO_RESOLVE = 0x3, - - /* A mask to mask the boolean status values off of instr->pass_flags */ - BRW_NIR_BOOLEAN_MASK = 0x3, -}; - -void brw_nir_analyze_boolean_resolves(nir_shader *nir); - struct brw_nir_compiler_opts { /* Soft floating point implementation shader */ const nir_shader *softfp64; diff --git a/src/intel/compiler/brw_nir_analyze_boolean_resolves.c b/src/intel/compiler/brw_nir_analyze_boolean_resolves.c deleted file mode 100644 index be9b79aa4b0..00000000000 --- a/src/intel/compiler/brw_nir_analyze_boolean_resolves.c +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright © 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "brw_nir.h" - -/* - * This file implements an analysis pass that determines when we have to do - * a boolean resolve on Gen <= 5. Instructions that need a boolean resolve - * will have the booleans portion of the instr->pass_flags field set to - * BRW_NIR_BOOLEAN_NEEDS_RESOLVE. - */ - - -/** Returns the resolve status for the given source - * - * If the source has a parent instruction then the resolve status is the - * status of the parent instruction. If the source does not have a parent - * instruction then we don't know so we return NON_BOOLEAN. - */ -static uint8_t -get_resolve_status_for_src(nir_src *src) -{ - nir_instr *src_instr = src->ssa->parent_instr; - uint8_t resolve_status = src_instr->pass_flags & BRW_NIR_BOOLEAN_MASK; - - /* If the source instruction needs resolve, then from the perspective - * of the user, it's a true boolean. - */ - if (resolve_status == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) - resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE; - return resolve_status; -} - -/** Marks the given source as needing a resolve - * - * If the given source corresponds to an unresolved boolean it marks it as - * needing a resolve. Otherwise, we leave it alone. - */ -static bool -src_mark_needs_resolve(nir_src *src, void *void_state) -{ - nir_instr *src_instr = src->ssa->parent_instr; - uint8_t resolve_status = src_instr->pass_flags & BRW_NIR_BOOLEAN_MASK; - - /* If the source instruction is unresolved, then mark it as needing - * to be resolved. - */ - if (resolve_status == BRW_NIR_BOOLEAN_UNRESOLVED) { - src_instr->pass_flags &= ~BRW_NIR_BOOLEAN_MASK; - src_instr->pass_flags |= BRW_NIR_BOOLEAN_NEEDS_RESOLVE; - } - - return true; -} - -static bool -analyze_boolean_resolves_block(nir_block *block) -{ - nir_foreach_instr(instr, block) { - switch (instr->type) { - case nir_instr_type_alu: { - /* For ALU instructions, the resolve status is handled in a - * three-step process. - * - * 1) Look at the instruction type and sources and determine if it - * can be left unresolved. - * - * 2) Look at the destination and see if we have to resolve - * anyway. (This is the case if this instruction is not the - * only instruction writing to a given register.) - * - * 3) If the instruction has a resolve status other than - * BOOL_UNRESOLVED or BOOL_NEEDS_RESOLVE then we walk through - * the sources and ensure that they are also resolved. This - * ensures that we don't end up with any stray unresolved - * booleans going into ADDs or something like that. - */ - - uint8_t resolve_status; - nir_alu_instr *alu = nir_instr_as_alu(instr); - switch (alu->op) { - case nir_op_b32all_fequal2: - case nir_op_b32all_iequal2: - case nir_op_b32all_fequal3: - case nir_op_b32all_iequal3: - case nir_op_b32all_fequal4: - case nir_op_b32all_iequal4: - case nir_op_b32any_fnequal2: - case nir_op_b32any_inequal2: - case nir_op_b32any_fnequal3: - case nir_op_b32any_inequal3: - case nir_op_b32any_fnequal4: - case nir_op_b32any_inequal4: - /* These are only implemented by the vec4 backend and its - * implementation emits resolved booleans. At some point in the - * future, this may change and we'll have to remove some of the - * above cases. - */ - resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE; - break; - - case nir_op_mov: - case nir_op_inot: - /* This is a single-source instruction. Just copy the resolve - * status from the source. - */ - resolve_status = get_resolve_status_for_src(&alu->src[0].src); - break; - - case nir_op_b32csel: - case nir_op_iand: - case nir_op_ior: - case nir_op_ixor: { - const unsigned first = alu->op == nir_op_b32csel ? 1 : 0; - uint8_t src0_status = get_resolve_status_for_src(&alu->src[first + 0].src); - uint8_t src1_status = get_resolve_status_for_src(&alu->src[first + 1].src); - - /* src0 of a bcsel is evaluated as a Boolean with the expectation - * that it has already been resolved. Mark it as such. - */ - if (alu->op == nir_op_b32csel) - src_mark_needs_resolve(&alu->src[0].src, NULL); - - if (src0_status == src1_status) { - resolve_status = src0_status; - } else if (src0_status == BRW_NIR_NON_BOOLEAN || - src1_status == BRW_NIR_NON_BOOLEAN) { - /* If one of the sources is a non-boolean then the whole - * thing is a non-boolean. - */ - resolve_status = BRW_NIR_NON_BOOLEAN; - } else { - /* At this point one of them is a true boolean and one is a - * boolean that needs a resolve. We could either resolve the - * unresolved source or we could resolve here. If we resolve - * the unresolved source then we get two resolves for the price - * of one. Just set this one to BOOLEAN_NO_RESOLVE and we'll - * let the code below force a resolve on the unresolved source. - */ - resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE; - } - break; - } - - default: - if (nir_alu_type_get_base_type(nir_op_infos[alu->op].output_type) == nir_type_bool) { - /* This instructions will turn into a CMP when we actually emit - * them so the result will have to be resolved before it can be - * used. - */ - resolve_status = BRW_NIR_BOOLEAN_UNRESOLVED; - - /* Even though the destination is allowed to be left - * unresolved, the sources are treated as regular integers or - * floats so they need to be resolved. - */ - nir_foreach_src(instr, src_mark_needs_resolve, NULL); - } else { - resolve_status = BRW_NIR_NON_BOOLEAN; - } - } - - /* Go ahead allow unresolved booleans. */ - instr->pass_flags = (instr->pass_flags & ~BRW_NIR_BOOLEAN_MASK) | - resolve_status; - - /* Finally, resolve sources if it's needed */ - switch (resolve_status) { - case BRW_NIR_BOOLEAN_NEEDS_RESOLVE: - case BRW_NIR_BOOLEAN_UNRESOLVED: - /* This instruction is either unresolved or we're doing the - * resolve here; leave the sources alone. - */ - break; - - case BRW_NIR_BOOLEAN_NO_RESOLVE: - case BRW_NIR_NON_BOOLEAN: - nir_foreach_src(instr, src_mark_needs_resolve, NULL); - break; - - default: - unreachable("Invalid boolean flag"); - } - - break; - } - - case nir_instr_type_load_const: { - nir_load_const_instr *load = nir_instr_as_load_const(instr); - - /* For load_const instructions, it's a boolean exactly when it holds - * one of the values NIR_TRUE or NIR_FALSE. - * - * Since load_const instructions don't have any sources, we don't - * have to worry about resolving them. - */ - instr->pass_flags &= ~BRW_NIR_BOOLEAN_MASK; - if (load->value[0].u32 == NIR_TRUE || load->value[0].u32 == NIR_FALSE) { - instr->pass_flags |= BRW_NIR_BOOLEAN_NO_RESOLVE; - } else { - instr->pass_flags |= BRW_NIR_NON_BOOLEAN; - } - continue; - } - - default: - /* Everything else is an unknown non-boolean value and needs to - * have all sources resolved. - */ - instr->pass_flags = (instr->pass_flags & ~BRW_NIR_BOOLEAN_MASK) | - BRW_NIR_NON_BOOLEAN; - nir_foreach_src(instr, src_mark_needs_resolve, NULL); - continue; - } - } - - nir_if *following_if = nir_block_get_following_if(block); - if (following_if) - src_mark_needs_resolve(&following_if->condition, NULL); - - return true; -} - -static void -analyze_boolean_resolves_impl(nir_function_impl *impl) -{ - nir_foreach_block(block, impl) { - analyze_boolean_resolves_block(block); - } -} - -void -brw_nir_analyze_boolean_resolves(nir_shader *shader) -{ - nir_foreach_function_impl(impl, shader) { - analyze_boolean_resolves_impl(impl); - } -} diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build index 1666844159c..481e72ac1a0 100644 --- a/src/intel/compiler/meson.build +++ b/src/intel/compiler/meson.build @@ -100,7 +100,6 @@ libintel_compiler_brw_files = files( 'brw_mesh.cpp', 'brw_nir.h', 'brw_nir.c', - 'brw_nir_analyze_boolean_resolves.c', 'brw_nir_analyze_ubo_ranges.c', 'brw_nir_attribute_workarounds.c', 'brw_nir_lower_cooperative_matrix.c',