From 9f3eb63878bbfd73e0c9112b5cec04caf930eb4d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20=C5=9Alusarz?= Date: Fri, 15 Jul 2022 13:43:21 +0200 Subject: [PATCH] Revert "nir/lower_task_shader: don't use base index for shared memory intrinsics" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit e5970fe22a66bf1727d8b677f4e3c93fe2172a71. Intel backend has implemented the missing functionality. Reviewed-by: Timur Kristóf Acked-by: Caio Oliveira Part-of: --- src/compiler/nir/nir_lower_task_shader.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/compiler/nir/nir_lower_task_shader.c b/src/compiler/nir/nir_lower_task_shader.c index 6112a5a6f12..b578a3949cf 100644 --- a/src/compiler/nir/nir_lower_task_shader.c +++ b/src/compiler/nir/nir_lower_task_shader.c @@ -55,7 +55,8 @@ lower_nv_task_output(nir_builder *b, case nir_intrinsic_load_output: { b->cursor = nir_after_instr(instr); nir_ssa_def *load = - nir_load_shared(b, 1, 32, nir_imm_int(b, s->task_count_shared_addr)); + nir_load_shared(b, 1, 32, nir_imm_int(b, 0), + .base = s->task_count_shared_addr); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, load); nir_instr_remove(instr); return true; @@ -64,7 +65,8 @@ lower_nv_task_output(nir_builder *b, case nir_intrinsic_store_output: { b->cursor = nir_after_instr(instr); nir_ssa_def *store_val = intrin->src[0].ssa; - nir_store_shared(b, store_val, nir_imm_int(b, s->task_count_shared_addr)); + nir_store_shared(b, store_val, nir_imm_int(b, 0), + .base = s->task_count_shared_addr); nir_instr_remove(instr); return true; } @@ -84,7 +86,7 @@ append_launch_mesh_workgroups_to_nv_task(nir_builder *b, */ b->cursor = nir_before_cf_list(&b->impl->body); nir_ssa_def *zero = nir_imm_int(b, 0); - nir_store_shared(b, zero, nir_imm_int(b, s->task_count_shared_addr)); + nir_store_shared(b, zero, zero, .base = s->task_count_shared_addr); nir_scoped_barrier(b, .execution_scope = NIR_SCOPE_WORKGROUP, @@ -104,7 +106,7 @@ append_launch_mesh_workgroups_to_nv_task(nir_builder *b, .memory_modes = nir_var_mem_shared); nir_ssa_def *task_count = - nir_load_shared(b, 1, 32, nir_imm_int(b, s->task_count_shared_addr)); + nir_load_shared(b, 1, 32, zero, .base = s->task_count_shared_addr); /* NV_mesh_shader doesn't offer to choose which task_payload variable * should be passed to mesh shaders, we just pass all.