diff --git a/src/panfrost/vulkan/panvk_vX_shader.c b/src/panfrost/vulkan/panvk_vX_shader.c
index 0c794996e47..22323fad4a6 100644
--- a/src/panfrost/vulkan/panvk_vX_shader.c
+++ b/src/panfrost/vulkan/panvk_vX_shader.c
@@ -387,9 +387,15 @@ valhall_pack_buf_idx(nir_builder *b, nir_instr *instr, UNUSED void *data)
        intrin->intrinsic != nir_intrinsic_load_ssbo)
       return false;
 
-   b->cursor = nir_before_instr(&intrin->instr);
    nir_def *index = intrin->src[0].ssa;
 
+   /* The descriptor lowering pass can add UBO loads, and those already have the
+    * right index format. */
+   if (index->num_components == 1)
+      return false;
+
+   b->cursor = nir_before_instr(&intrin->instr);
+
    /* The valhall backend expects nir_address_format_32bit_index_offset,
     * but address mode is nir_address_format_vec2_index_32bit_offset to allow
     * us to store the array size, set and index without losing information